This page gives overview of Video Processing Subsystem which is available as part of the Xilinx Vivado and SDK distribution.
The Subsystem is divided into 5 drivers -
1. v_hscaler - Horizontal scaler
2. v_vscaler - Vertical scaler
3. v_hcresampler - Horizontal chroma resampler
4. v_vcresampler - Vertical chroma resampler
5. v_csc - Color space converter

How to enable

1. v_hscaler -
2. v_vscaler -
3. v_hcresampler -
4. v_vcresampler -
5. v_csc -

Driver source code is organized into different folders. Below diagram shows the driver source organization

-- Doc - Provides the API and data structure details
- Examples - Reference application to show how to use the driver APIs and calling sequence
- Source - Driver source files

Supported Features

The following features are supported:

  • One, two, or four pixel-wide video interface
  • Run-time color space support for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0
  • 8, 10, 12, and 16 bits per component support
  • Deinterlacing
  • Scaling
  • Color space conversion and correction
  • Chroma resampling between YUV 4:4:4, YUV 4:2:2, YUV 4:2:0
  • Frame rate conversion
  • Supports resolutions up to 4096 x 2160

Test Procedure

The example application contains an example on how to use the XVprocss driver directly.
Contains a tcl file which automates the process of generating the downloadable bit & elf
files from the provided example hdf file. Example application design source files
(contained within "examples/src" folder) are tightly coupled with the video processing
subsystem example design available in Vivado Catalogue.
To run this tcl
1. Copy the exported example design hdf file in the "examples" directory of the driver
2. Launch the xsct terminal
3. cd into the examples directory
4. source the tcl file
@code xsct%>source vpss_example.tcl @endcode
5. execute the script
@code xsct%>vpss_example <hdf_file_name.hdf> @endcode
Script will perform following operations
1. Create workspace
2. Create HW project
3. Create BSP
4. Create Application Project
5. Build BSP and Application Project
After the process is complete required files will be available in
bit file -> vpss_example.sdk/vpss_example_hw_platform folder
elf file -> vpss_example.sdk/vpss_example_design/{Debug/Release} folder
When executed on the board the example application will determine the video
processing subsystem topology and set the input and output stream
configuration accordingly. Test pattern generator IP is used to generate
the input stream. Video Lock Monitor IP will then monitor the output of
the subsystem (to vidout) to determine if lock is achieved and present the
status (Pass/Fail) on the terminal.
@note Serial terminal baud rate should be set to 115200