Document History

Date
Version
Author
Description of Revisions
April 30, 2014
0.1
E.Srikanth
Initial Posting

Acknowledgement:

Thanks to Ken Chapman for the core code contributions.

Description


This techtip is an extension to the Zynq-7000 All Programmable SoC- Installing and running the Power Demo Tech-tip. This techtip describes the Programmable Logic Design used to consume power on the programmable logic to facilitate power measurements on the ZC702 Board.

The design used to configure the PL logic is based on the XAPP555 Power Demo reference design used to measure power for Virtex-7 FPGAs. Since the 7-series devices do not have a processor, the power measurements have been done using a master Picoblaze processor controlling multiple Picoblaze based Power Consuming Modules and Speed test modules (PCASTM) connected in a daisy chain fashion. In the Zynq Power Demo the master Picoblaze processor has been replaced with Zynq Processing system and other components like DLNA and VID testing has been removed.

The Zynq Power measurements are performed by power regulators from Texas Instruments on the ZC702 board which is PMBus compliant. The Zynq-7000 device reads the power measurement via the I2C interface. The information on Zynq Power Measurements is described in detail in Zynq-7000 AP SoC Measuring ZC702 Power using Linux Application Tech Tip.

The design files for this techtip can be downloaded here: Zynq7000_AP_SoC_Power_Demo_PL_design.zip


Implementation

Implementation Details
Design Type
PS & PL
SW Type
Linux
CPUs
Dual Cortex-A9 cores
PS Features
MAXI-GP0
PL Cores
UART-Lite, AXI Interconnect, PCASTM Chain
Boards/Tools
ZC702
Xilinx Tools Version
Vivado 2014.1
Other Details
None

Files Provided
Zynq7000_AP_SoC_Power_Demo_PL_design.zip
Archived Vivado project

Design Details

The reference design was originally designed by Ken Chapman and has been modified to measure power for the ZC702 board.
The PL Based design for Zynq Power Demo consists of the following blocks.
  1. Zynq Processing System
  2. AXI UART Lite
  3. PCASTM Chain

Figure 1 Zynq PL Based Power Demo.PNG
Figure 1: Zynq PL Based Power Demo



The PCASTM Chain consists of Multiple PCASTM modules connected in a chain of whatever length is desired and which can fit into the target device. Each PCASTM is formed of two sections; a ‘Power Consuming’ section and a ‘Speed Test’ section. The speed test will also result in the consumption of additional power.
‘Speed Test’ – The speed test is operated at a higher clock frequency (‘fast_clk’) and is intended to verify the ability of the device to exceed the specified design performance. The speed test requires that logic functions within each module operate correctly at each frequency and also that the ‘enable’ and 8-bit ‘number’ signals all have less than single clock cycle propagation times. As soon as one path is too slow for the clock frequency the incorrect operation will be detected and hence reveal the maximum performance of the speed test circuits in the given device (P) at that voltage (V) and temperature (T).
Control and ‘Power Consuming’ Logic – The PCASTM module consists of a Picoblaze processor which can control the 16 toggle flip-flops, the 16-bit LFSR counter and the 16-bit accumulator in any combination. The Picoblaze processor can also be kept in sleep mode if required. This has been done to increase or decrease dynamic power consumption by controlling any of the blocks in the PCASTM module. The PCASTM blocks also include a UART module running at 115200 baud rate through which can receive and transmit ASCII commands to or from the Zynq Processing system or to the next PCASTM module in the chain. This scheme provides flexibility and scalability whilst only requiring one wire to link each pair of modules, which in turn, allows the links of the speed test to dominate the connectivity between modules.
  • Figure 2 PCAST Module Block Diagram.PNG
    Figure 2: PCAST Module Block Diagram


The Power Consuming and Speed Test Modules (PCASTM) modules are connected in a chain of whatever length is desired and which can fit into the target device. For ease of design manipulation a constant called ‘pcast_chain_length’ has been defined and is used to define the number of PCASTM in the chain without requiring any additional changes to be needed. This illustration shows a chain formed of only 3 modules but it would be more normal to have hundreds or even thousands in a large device.

  • Figure 3 PCASTM connected in chain.PNG
    Figure 3: PCASTM connected in chain

The majority of the circuits operate at 100MHz but the speed test involves sweeping the variable clock to determine the maximum performance of the 8-bit speed test circuits. This supplied by the FPGA Clock 1 pin of the Zynq Processing System. In the uirrent design the ZC702 is capable of ruuning 256 PCASTM modules to achieve 99% LUT and 85% BRAM uitlization.

PCASTM Commands


The commands currently implemented by PicoBlaze inside each PCASTM are all formed of readable ASCII characters. A command always begins with the # character. All PCASTM will remain in ‘echo mode’ until the # character is encountered.
Although a # character will also be echoed, PicoBlaze will transition into a ‘command mode’ in which the next character will define the command, and when relevant, further characters will provide information to be used with that command. When in the command mode PicoBlaze will remain permanently awake. Once a command has been processed, PicoBlaze will return to the ‘echo mode’ and may go to sleep if it is set to be in the sleep mode.

Though the PCASTM supports multiple commands, the software application in the current Power demo uses only the following commands to control the PCASTM chain.
ASCII
Command
Description
#T
Transparent Command
This command forces the PCASTM back into ‘echo mode’ immediately
#Eaaaa
Enumerate Command
The enumerate command is the way to assign a unique address to each module. In most applications the command sent to the chain specifies an address of zero (specified using the 4-digit hex representation ‘0000’). As this is received by the first module the address value is incremented to ‘0001’ and becomes the address of that module. It then transmits its own address to the next module. Hence the address increment as it ripples through the chain.
The message observed at the end of the chain reveals the number of modules in the chain. This is how the master can report the number of
modules without being specifically programmed
#Clllluuuubbbb
Control Command
This command enables up to 16 control bits to be set as required in one or more PCASTM in the chain. The command string passes unaltered through each module to re-emerge at the end. As each module receives and echoes the control command it decides if the command should be applied to it and updates the control value with the specified value if it should. Please refer to the XAPP555 reference design presentation for details of the Command and Status Bits.
#Olllluuuussss
‘OR’ Status Command
This ‘OR’ status command allows the 16 status bits of one or more PCASTM in the chain to be observed. In other words, it is possible to use this command to observe the status word of just one particular module or to observe the combined status of many or all modules in one go. Please refer to the XAPP555 reference design presentation for details of the Command and Status Bits
#I
Initialize Command
This command will ripple all the way through the chain and cause all modules to revert to the initial default state. This is the lowest power state in which all power consuming peripherals are disabled, the speed test LFSR counter is held in reset and KCPSM6 will be sleeping. All modules will also revert to their default address of ‘0000’ so the enumerate command would normally be used again afterwards.

Please refer to the PCASTM Command reference in XAPP555 reference design presentation present in "C:\ Zynq7000AP_SoC_ Power_Demo_design\" directory in the downloaded design files for all the commands supported.

Step by Step Instructions


ZC702 Board Setup


Following are requirements for setting up ZC702 board for power demo:
  • ZC702 board and related power supply
  • 8GB and above SD Card to hold executable
  • USB to Mini USB for USB-UART
  • PC

Connect an USB Mini-B cable into the Mini USB port J17 labeled USB UART on the ZC702 board and the USB Type-A cable end into an open USB port on the host PC for UART communications.
Connect the power supply to the ZC702 board. Do not switch the power on.
Make sure the switches are set as shown in figure below, which allows the ZC702 board to boot from the SD-MMC card
Figure 4 Setting the Bootstraps to boot from SDcard.PNG
Figure 4: Setting the Bootstraps to boot from SDcard

A "ready_to_test" directory has already been provided, if you wish to use the ready to test files you can directly refer to Running the Design Section of this document.

Generating the Hardware Design

  1. Copy the Zynq7000AP_SoC_ Power_Demo_design.zip file to your hard drive and unzip the file to C drive.
  2. Open the Vivado GUI.
  3. Select Open Project to open the existing project.
  4. Browse to the C:\ Zynq7000AP_SoC_ Power_Demo_design\design\power_001” folder where the vivado project is present.
  5. Select the power_001.xpr file and select ok.
  6. The Vivado tool should show the project open.
  7. In the Source View under Design Sources, expand the zynq_power_top.vhd file.
    Figure 4 Design Hierarchy.PNG
    Figure 4: Design Hierarchy for PL Design
  8. Double click on the zynq_platform.bd file to open the Zynq Block design. And check the inter-connectivity as shown below
    Figure 5 Zynq Block Design_se.PNG
    Figure 5: Zynq Block Design
  9. Ensure that the zynq_power_top.vhd file is selected as the top module under Design sources, click on the Program and Debug à Generate Bitstream to generate the bit stream.
    Figure 6 Generating the Bitstream_se.PNG
    Figure 7: Generating the Bitstream
  10. The Vivado tool will prompt that synthesis and implementation results are not available and would ask to run the synthesis and implementation process.
  11. Click Yes and vivado tool would run the Synthesis and implementation process and finally generate the bitstream.
  12. After the bitstream is generated. Select View report in Bitstream generated successfully dialog box and click OK.
  13. In the Vivado tool, select Fileà Exportà Export Hardware design to SDK.
    Figure 7 Exporting the Hardware to SDK_se.PNG
    Figure 8: Exporting the Hardware to SDK
  14. Ensure that Export Hardware, Include bitstream and Launch SDK options are checked and click ok.
  15. The Vivado tool will export the hardware and bitstream to SDK and finally SDK tool is launched.

Compiling the Linux application.
  1. In the SDK tool, Select File > New > Application Project.
    Figure 8 Creating a C Application Project_se.PNG
    Figure 9: Creating a C Application Project
  2. In the Project name field, enter power_demo.
  3. Select Linux as the OS platform.
  4. Click Next.
    Figure 9 Naming the C Project and Selecting a Project Type_se.PNG
    Figure 10: Naming the C Project and Selecting a Project Type
  5. Select Linux Empty Application as the project template.
  6. Click Finish.
    Figure 10 Selecting the Linux Application Template_se.PNG
    Figure 11 Selecting the Linux Application Template
  7. Import the simple pl_power_demo application that has been provided.
  8. In the Project Explorer tab, expand the power_demo project, right-click the src folder, and select Import.
  9. In theSelect dialog box, expand General, select File System,and click Next.
    Figure 11 Importing Files into the Project_se.PNG
    Figure 12: Importing Files into the Project
  10. In the From directory field,browse to the C:\ Zynq7000AP_SoC_ Power_Demo_design\sw\src directory and click OK.
  11. Select pl_power_demo.c and i2c-dev.h for import.
    Use the default Into folderdirectory path, which copies the files into the current project.
    Figure 12 Importing Existing Source Files into the Application_se.PNG
    Figure 13: Importing Existing Source Files into the Application
  12. Click Finish.
    The project will be automatically built. After the application is built, the Console window shows the results of the build.
  13. You should see an error during the compilation indicating that it is unable to determine the pow() function. This is because the SDK is not able to search the math library in its compilation path.
  14. In the Project Explorer tab, right click on the power_demo project and select C/C++ BUILD Settings.
  15. In the power_demo settings dialog, select Libraries under ARM Linux gcc linker.
  16. Add the math library by selecting the add button in the Libraries section and enter’m’ and click ok.
    Figure 13 Adding the math library_se.PNG
    Figure 14: Adding the math library
  17. Now the SDK builds the application successfully.
  18. The power_demo.elf is successfully build into “C:\ Zynq7000AP_SoC_ Power_Demo_design\design\power_001\power_001.sdk\SDK\SDK_Export\power_demo\Debug” directory.
  19. Make sure that the application is built without errors.
  20. In the Project Explorer tab, expand power_demo-->src and open the pl_power_demo.c file.
  21. Carefully observe the code and look at the code comments to understand what each function is doing in the C file.

Create the First Stage Boot Loader Executable File

  1. In SDK, select File > New > Application Project.
    The New Project wizard opens.
    Use the information in the table below to make your selections in the wizard screens.
Wizard Screen
System Property
Setting or Command to Use
Application Project
Project Name
fsbl
Use Default Location
Select this option
Hardware Platform
hw_platform_0
Processor
PS7_cortexa9_0
OS Platform
Standalone
Language
C
Board Support Package
Select Create New and provide the name of fsbl_bsp.
Templates
Available Templates
Zynq FSBL
  1. Click Finish. The New Project Wizard closes.
  2. In the fsbl BSP ensure that the console is set to ps7_uart1.
  3. Right click the fsbl_bsp folder and select BSP settings . In the BSP settings dialog , select standalone and check if the std-in and std-out is set to ps7_uart1. If it is not , then set it to ps7_uart1 and rebuild the fsbl application and bsp.
  4. SDK creates the fsbl application project and the fsbl_bsp BSP project under the project explorer. SDK also automatically compiles the project and generates the fsbl.elf file.

Building Linux Components

This section describes how to build Linux specific components i.e. the second stage boot loader u-boot, the Linux kernel image and device tree blob, and the Linux root file system. To complete this section, you are required to have a Linux development PC with the ARM GNU cross compile tool chain and the Git tool installed. Make sure you have your PATH and CROSS_COMPILE environment variables set correctly. You can use the corkscrew tool if you are having difficulties accessing Xilinx git repositories from behind a firewall.

Building the u-boot Second Stage Boot Loader

This section explains how to download the sources, configure, and build the u-boot second stage boot loader. For additional information, refer to theXilinx Zynq u-boot wiki
The prebuilt u-boot image is present in the “C:\Power_Demo\sw\images” directory.
  1. Clone the latest Zynq u-boot git repository from the Xilinx git server.
    $ git clone git://github.com/xilinx/u-boot-xlnx.git
    $ cd u-boot-xlnx
Configure u-boot for the Zynq ZC702.
  1. Build the u-boot boot loader. The generated U-boot executable can be found at u-boot-xlnx/u-boot.
    $ make ARCH=arm zynq_zc70x_config
    $ make ARCH=arm
  2. Rename the u-boot executable to u-boot.elf.
    $ mv u-boot u-boot.elf

Building the Linux kernel image with axi-uart-lite driver

This section explains how to download the sources, configure, include the axi-lite driver and build the Linux kernel image and the device tree blob. For additional information, refer to the Xilinx Zynq Linux wiki.
  1. Clone the Zynq Linux kernel version xilinx-v14.7 from Xilinx server repository.
    $ git clone git://github.com/xilinx/linux-xlnx.git
    $ cd linux-xlnx
    $ git checkout –b zynq_power xilinx-v14.7
  2. Configure the Linux kernel.
    $ make ARCH=arm xilinx_zynq_defconfig
    $ make ARCH=arm menuconfig
  3. This will open the kernel configuration.
  4. Include the uart-lite driver to the Linux kernel.
    In the kernel configuration menu go to Device drivers à Character DevicesàSerial drivers and check Xilinx uartlite serial port for built-in support. Please do not check the Support for console Xilinx uartlite serial port option.
  5. Save the linux kernel configuration and exit
  6. Build the Linux kernel. The generated kernel image can be found at linux-xlnx/arch/arm/boot/uImage
    $ make ARCH=arm uImage modules UIMAGE_LOADADDR=0x8000

Adding the AXI UART-Lite to ZC702 Device tree and compiling it.

The device tree for the ZC702 base platform zynq-zc702.dts is present in /arch/arm/boot/dts/”directory.
  1. Open the ZC702 base platform device tree using gedit or vi editor
  2. Add the following instance to the zynq-zc702.dts file after the ps7-xadc instance in the dts file
    axi_uartlite_0: serial@42c00000 {
                           clock-frequency = <100000000>;
                           clocks = <&clkc 15>;
                           compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a";
                           current-speed = <921600>;
                           device_type = "serial";
                           interrupt-parent = <&ps7_scugic_0>;
                           interrupts = <0 59 1>;
                           port-number = <2>;
                           reg = <0x42c00000 0x10000>;
                           xlnx,baudrate = <0xe1000>;
                           xlnx,data-bits = <0x8>;
                           xlnx,odd-parity = <0x0>;
                           xlnx,s-axi-aclk-freq-hz-d = <0x64>;
                           xlnx,use-parity = <0x0>;
                           } ;
  3. Save and compile the ZC702 base platform device tree file.
    $ ./scripts/dtc/dtc -I dts -O dtb -o devicetree.dtb ./arch/arm/boot/dts/zynq-zc702.dts
  4. The output of this step is a device tree blob which can be found at linux-xlnx/devicetree.dtb.

Make a Linux Bootable Image for SD CARD

  1. In SDK, select Xilinx Tools > Create Zynq Boot Image.
    The Create Zynq Boot Image wizard opens.
  2. Provide the fsbl.elf path in the FSBL ELF tab.
    Note: You can find fsbl.elf in “Zynq7000AP_SoC_ Power_Demo_design\design\power_001\power_001.sdk\SDK\SDK_Export\fsbl\Debug” directory.
  3. Add the system.bit file present in “Zynq7000AP_SoC_ Power_Demo_design\design\power_001\power_001.sdk\SDK\SDK_Export\hw_platform_0” directory.
  4. Add the U-Boot image present in present in “Zynq7000AP_SoC_ Power_Demo_design\sw\images”directory.
  5. Select the appropriate output directory and Click Create Image.
  6. The Create Zynq Boot Image window creates the BOOT.bin in the specified output directory which is the boot image for the SD card.
  7. Copy the BOOT.bin, device tree.dtb, uImage files to the SD card.
  8. Copy the uramdisk.image.gz file from C:\Zynq7000AP_SoC_ Power_Demo_design\ready_to_test directory to the SDcard.
  9. Copy the power_demo.elf file from C:\ Zynq7000AP_SoC_ Power_Demo_design\design\power_001\power_001.sdk\SDK\SDK_Export\power_demo\Debug”directory to SDCard.

Running the Design

  1. Insert the SD-MMC memory card, which contains the binaries and the power_demo.elf file, into the SD slot on the ZC702 board.
    User can optionally use the ready_to design files to run the design if he wants to avoid the above steps
  2. Open a Serial Terminal (Like Hyperterminal or Teraterm) configured at following settings to view the serial messages of the ZC702.
    • Baudrate: 115200
    • No of bit s: 8
    • Parity : 1
    • Flow Control : NONE
  3. Power on the ZC702 board.
    Wait for the ZC702 board to be configured and booted with Linux.
  4. cd to the /mnt directory and execute the power_demo.elf file.
    $ cd /mnt
    $ ./powertop.elf
  5. Observe the messages in the Serial console
    Figure 14 Serial messages for the PL Power Demo_se.PNG
    Figure 15: Serial messages for the PL Power Demo
  6. The serial console will display the list of commands that can be executed to measure the PL Power.
  7. The list of commands is as mentioned below. Try to manually play with the different command to control the pcastm chain and measure the power
0 – Turn off all Picoblazes in PCASTM chain
9 – Set clock speed to 200MHz to Speed chain in PCASTM
1 – Turn 64 Picoblazes ON in PCASTM chain
b – Set clock speed to 200MHz to Speed chain in PCASTM if turned off
2 – Turn 128 Picoblazes ON in PCASTM chain
t -- Enable/Disable Toggle Flip Flops in PCASTM Chain
3 – Turn 192 Picoblazes ON in PCASTM chain
c -- Enable/Disable LFSR Counters in PCASTM Chain
4 – Turn all(256) Picoblazes ON in PCASTM chain
a -- Enable/Disable Accumulator in PCASTM Chain
5 – Turn off clock to Speed chain in PCASTM
z -- Force PL to Low Power Mode
6 – Set clock speed to 50MHz to Speed chain in PCASTM
w -- Wake PL from Low Power Mode
7 – Set clock speed to 100MHz to Speed chain in PCASTM
x – Read Power Status
8 – Set clock speed to 150MHz to Speed chain in PCASTM
s -- Read PCASTM Status
Table 1 List of Commands

Conclusion:
This techtip describes the Programmable Logic Design used to consume power on the programmable logic to facilitate power measurements on the ZC702 Board. This tech tip has also demonstrated on how to use the measure the power on the ZC702 board as well as perform some PL power management features.