Introduction

ZynqMP SoC has a Serdes/SIOU(Serial Input and Output block) module which provides High Speed Physical interface
for the below High Speed peripherals present in the SoC
  1. USB (2 controllers)
  2. SATA (1 controller with two lanes)
  3. Display Port (1 controller with two lanes)
  4. SGMII (4 controllers)
  5. PCIe (1 controller with four lanes)
The inputs to Serdes is PIPE interface and output from it is are four High speed serial lanes. PHY provides 4 output lanes only for 14(PIPE) inputs (as mentioned above: 2 + 2 + 4 + 2+ 4 = 14). All the inputs are routed to PHY output lanes with a Mux (Interconnect matrix). Only some combinations are valid i.e, one cannot set Mux to use USB1 on lane 0 as such. PHY driver validates dts entries for the correct combination of controller and serdes lanes. Below the interconnect matrix which shows valid combinations:

HW/IP Features

The ZynqMP PS shall incorporate a quad GT. Features include
  • A quad-transceiver
  • Supports PCIe, SATA, USB3.0, SGMII and DisplayPort requirements
  1. 1,2, or 4 lane PCIe support at 2.5 or 5.0Gbps
  2. 1 or 2 lane DisplayPort (TX only) at 1.62, 2.7, or 5.4Gbps
  3. 1-2 SATA channels at 1.5, 3.0 or 6.0Gbps
  4. 1-2 USB3.0 channel at 5.0Gbps
  5. 1-4 Ethernet SGMII channels at 1.25Gbps
  • Support SGMII for data only (no clock, or clock optional)
  • Support any 4 of the standards simultaneously
  • Provide flexible host-programmable multiplexing function for connecting the GT resources to the PS masters (DisplayPort, PCIe, SATA, GEM).

Kernel Configuration

Device Drivers------>
     Phy Subsystem-->
         <*> Xilinx ZynqMP phy driver
 
By enabling the above we need to see the below mentioned Kconfig parameter enabled
CONFIG_PHY_XIILINX_ZYNQMP=y

Devicetree

Device nodes should specify the configuration required in their "phys" property, containing a phandle to the phy port node and a device type
The phys property should be as mentioned below:

phys = <PHANDLE CONTOLLER_TYPE CONTROLLER_INSTANCE LANE_NUM LANE_FREQ>;

PHANDLE can be any among &lane0 or &lane1 or &lane2 or &lane3

CONTROLLER_TYPE can be any among PHY_TYPE_PCIE or PHY_TYPE_SATA or PHY_TYPE_USB or PHY_TYPE_DP or PHY_TYPE_SGMII

CONTROLLER_INSTANCE depends on CONTROLLER TYPE used, can be any of below

PHY_TYPE_PCIE : 0 or 1 or 2 or 3

PHY_TYPE_SATA : 0 or 1

PHY_TYPE_USB : 0 or 1

PHY_TYPE_DP : 0 or 1

PHY_TYPE_SGMII: 0 or 1 or 2 or 3
LANE_NUM depends on which lane clock is used as ref clk, can be 0 or 1 or 2 or 3

LANE_FREQ is the Frequency that controller can operate, can be any among 19.2Mhz,20Mhz,24Mhz,26Mhz,27Mhz,28.4Mhz,40Mhz,52Mhz,100Mhz,108Mhz,125Mhz,135Mhz,150Mhz

Example
Below Code should is required for probing the serdes driver. This should be added in zynqmp.dtsi
serdes: zynqmp_phy@fd400000 {
    compatible = "xlnx,zynqmp-psgtr";
    status = "okay";
    reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>,
        <0x0 0xfd1a0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>;
    reg-names = "serdes", "siou", "fpd", "lpd";
    xlnx,tx_termination_fix;
 
    lane0: lane@0 {
        #phy-cells = <4>;
    };
    lane1: lane@1 {
        #phy-cells = <4>;
    };
    lane2: lane@2 {
        #phy-cells = <4>;
    };
    lane3: lane@3 {
        #phy-cells = <4>;
    };
};

The below code configures the USB 0 instance to use lane 2 and get 26 MHZ lane refclk from lane 2.
usb@fe200000 {
    ...
    phys = <&lane2 PHY_TYPE_USB3 0 2 2600000>;
    ...
};

This below code configures the SATA 1 instance to use lane 3 and get 125MHZ lane refclk from lane 1.
ahci@fd0c0000 {
    ...
    phys      = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
    ...
};

Test Procedure

As this driver is being used by SATA, USB, PCIe, SGMII and DP protocols. Testing the functionality any of those protocols will automatically test this IP.

Expected O/P

Once linux is booted type "grep | gtr" and check whether PLL lock is happening , the below output is expected
root@Xilinx-ZCU102-2016_3:~# dmesg | grep gtr
[    6.575387] xilinx-psgtr fd400000.zynqmp_phy: Lane:3 type:3 protocol:2 pll_locked:yes
[    6.808627] xilinx-psgtr fd400000.zynqmp_phy: Lane:2 type:0 protocol:3 pll_locked:yes
[    7.570858] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:yes

Mainline Status

The driver is not yet upstreamed into mainline kernel

Change log

2016.3
Summary:
  • Correct swing and preemphasis values
  • Reset the de-emphasis and swing control for DP
  • Added separate function for bypassing scrambler/descrambler and encoder/decoder feature
  • Add SGMII support to serdes driver
  • Fix kernel-doc format for xpsgtr_set_rxwidth
  • Add missing header to declare exported functions
  • Change serdes calibraton logic to ICM_CFG1
Commits:
ffdbb29
aabcb4
4e8a03
c1212e
bef32e
3f3097
c1c13c

2016.4
Summary:
  • NONE

2017.1
Summary:
  • Removed tx_termination_fix flag and added the calibration fix based on the silicon revision
  • Use reset-controller framework to assert/de-assert reset signals while configuring serdes lanes
  • Corrected the logic for freeing NVMEM buffer
  • Corrected the logic for waitng for assert/de-assert to happen
  • Added configuring USB PIPE3 signals during reset release
Commits:
27aa0
9b4ee
330ed
d52db
88c55


2017.2
Summary:
  • None

2017.3
Summary:
  • Use the configured GT lane instead of hardcoding a value into ICM_CFG1 for tx termination fix
Commits:
ebbed

2017.4
Summary:
  • Export functions for asserting/de-asserting usb core reset
Commits:
52f8f

2018.1
Summary:
  • Reinitialize gt lane for USB only if required
  • Use EEMI framework for performing ULPI reset sequence
Commits:
6d786
f366d

2018.2
Summary:
  • None

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