{"type":"doc","content":[{"type":"paragraph","content":[{"text":"Table of Contents","type":"text","marks":[{"type":"strong"}]}]},{"type":"extension","attrs":{"layout":"default","extensionType":"com.atlassian.confluence.macro.core","extensionKey":"toc","parameters":{"macroParams":{},"macroMetadata":{"macroId":{"value":"bb42c011-cbee-4e03-a9aa-d9e2731ff7da"},"schemaVersion":{"value":"1"},"title":"Table of Contents"}},"localId":"29e273b1-cf11-4ed6-a48e-6c1bf1656b5e"}},{"type":"heading","attrs":{"level":1},"content":[{"text":"Introduction","type":"text"}]},{"type":"paragraph","content":[{"text":"ZynqMP SoC has a Serdes/SIOU(Serial Input and Output block) module which provides High Speed Physical interface","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":"for the below High Speed peripherals present in the SoC","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"USB (2 controllers)","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"SATA (1 controller with two lanes)","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Display Port (1 controller with two lanes)","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"SGMII (4 controllers)","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"PCIe (1 controller with four lanes)","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]}]}]},{"type":"paragraph","content":[{"text":"The inputs to Serdes is PIPE interface and output from it is are four High speed serial lanes. PHY provides 4 output lanes only for 14(PIPE) inputs (as mentioned above: 2 + 2 + 4 + 2+ 4 = 14). All the inputs are routed to PHY output lanes with a Mux (Interconnect matrix). Only some combinations are valid i.e, one cannot set Mux to use USB1 on lane 0 as such. PHY driver validates dts entries for the correct combination of controller and serdes lanes.","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]},{"type":"paragraph","content":[{"text":"Note:","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}},{"type":"strong"}]}]},{"type":"paragraph","content":[{"text":"Due to the new driver introduce in upstream flow, we have (kernel and devicetree flow) configurations based on the release:","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Support till 2020.2 release","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Support form 2021.1 release","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]}]}]},{"type":"paragraph","content":[{"type":"hardBreak"}]},{"type":"paragraph","content":[{"text":"HW/IP Features","type":"text","marks":[{"type":"textColor","attrs":{"color":"#172b4d"}}]}]},{"type":"paragraph","content":[{"text":"The ZynqMP PS shall incorporate a quad GT. Features include","type":"text"},{"type":"hardBreak"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"A quad-transceiver","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Supports PCIe, SATA, USB3.0, SGMII and DisplayPort requirements","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"1,2, or 4 lane PCIe support at 2.5 or 5.0Gbps","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"1 or 2 lane DisplayPort (TX only) at 1.62, 2.7, or 5.4Gbps","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"1-2 SATA channels at 1.5, 3.0 or 6.0Gbps","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"1-2 USB3.0 channel at 5.0Gbps","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"1-4 Ethernet SGMII channels at 1.25Gbps","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Support SGMII for data only (no clock, or clock optional)","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Support any 4 of the standards simultaneously","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Provide flexible host-programmable multiplexing function for connecting the GT resources to the PS masters (DisplayPort, PCIe, SATA, GEM).","type":"text"}]}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Kernel Configuration","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Support till 2020.2 release","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"text":":","type":"text"}]},{"type":"codeBlock","content":[{"text":"Device Drivers------>\n Phy Subsystem-->\n <*> Xilinx ZynqMP phy driver\n ","type":"text"}]},{"type":"paragraph","content":[{"text":"By enabling the above we need to see the below mentioned Kconfig parameter enabled","type":"text"},{"type":"hardBreak"},{"text":"CONFIG_PHY_XIILINX_ZYNQMP=y","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Support form 2021.1 release","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"text":":","type":"text"}]},{"type":"codeBlock","content":[{"text":"Device Drivers------>\n Phy Subsystem-->\n\t\t-*- PHY Core\n -*- Xilinx ZynqMP PHY driver ","type":"text"}]},{"type":"paragraph","content":[{"text":"By enabling the above we need to see the below mentioned Kconfig parameter enabled","type":"text","marks":[{"type":"backgroundColor","attrs":{"color":"#ffffff"}}]}]},{"type":"paragraph","content":[{"text":"CONFIG_PHY_XILINX_ZYNQMP=y","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Devicetree","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Support till 2020.2 release","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"text":":","type":"text"}]},{"type":"paragraph","content":[{"text":"Device nodes should specify the configuration required in their \"phys\" property, containing a phandle to the phy port node and a device type","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":"The phys property should be as mentioned below:","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"type":"hardBreak"},{"text":"phys = ;","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":"PHANDLE can be any among &lane0 or &lane1 or &lane2 or &lane3","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":"CONTROLLER_TYPE can be any among PHY_TYPE_PCIE or PHY_TYPE_SATA or PHY_TYPE_USB or PHY_TYPE_DP or PHY_TYPE_SGMII","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":"CONTROLLER_INSTANCE depends on CONTROLLER TYPE used, can be any of below","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"type":"hardBreak"},{"text":"PHY_TYPE_PCIE : 0 or 1 or 2 or 3","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":"PHY_TYPE_SATA : 0 or 1","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":" PHY_TYPE_USB : 0 or 1","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":" PHY_TYPE_DP : 0 or 1","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":" PHY_TYPE_SGMII: 0 or 1 or 2 or 3","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]}]}]}]},{"type":"paragraph","content":[{"type":"hardBreak"},{"text":"LANE_NUM depends on which lane clock is used as ref clk, can be 0 or 1 or 2 or 3","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"text":"LANE_FREQ is the Frequency that controller can operate, can be any among 19.2Mhz,20Mhz,24Mhz,26Mhz,27Mhz,28.4Mhz,40Mhz,52Mhz,100Mhz,108Mhz,125Mhz,135Mhz,150Mhz","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"},{"type":"hardBreak"},{"text":"Example","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}},{"type":"strong"}]},{"type":"hardBreak"},{"text":"Below Code should is required for probing the serdes driver. This should be added in zynqmp.dtsi","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"}]},{"type":"codeBlock","content":[{"text":"serdes: zynqmp_phy@fd400000 {\n compatible = \"xlnx,zynqmp-psgtr\";\n status = \"okay\";\n reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>,\n <0x0 0xfd1a0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>;\n reg-names = \"serdes\", \"siou\", \"fpd\", \"lpd\";\n xlnx,tx_termination_fix;\n \n lane0: lane@0 {\n #phy-cells = <4>;\n };\n lane1: lane@1 {\n #phy-cells = <4>;\n };\n lane2: lane@2 {\n #phy-cells = <4>;\n };\n lane3: lane@3 {\n #phy-cells = <4>;\n };\n};","type":"text"}]},{"type":"paragraph","content":[{"type":"hardBreak"},{"text":"The below code configures the USB 0 instance to use lane 2 and get 26 MHZ lane refclk from lane 2.","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"}]},{"type":"codeBlock","content":[{"text":"usb@fe200000 {\n ...\n phys = <&&lane2 PHY_TYPE_USB3 0 2 2600000>;\n ...\n};","type":"text"}]},{"type":"paragraph","content":[{"type":"hardBreak"},{"text":"This below code configures the SATA 1 instance to use lane 3 and get 125MHZ lane refclk from lane 1.","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"}]},{"type":"codeBlock","content":[{"text":"ahci@fd0c0000 {\n ...\n phys = <&&lane3 PHY_TYPE_SATA 1 1 125000000>;\n ...\n};","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Support form 2021.1 release","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"text":":","type":"text"}]},{"type":"paragraph","content":[{"text":"In the new upstreamed flow the below are the changes that need to be added ","type":"text"}]},{"type":"paragraph","content":[{"text":"phys = ;","type":"text"}]},{"type":"paragraph","content":[{"text":"PHANDLE = &psgtr","type":"text"}]},{"type":"paragraph","content":[{"text":"LANE_NUM = 0, 1, 2, 3","type":"text"}]},{"type":"paragraph","content":[{"text":"CONTOLLER_TYPE = PHY_TYPE_PCIE or PHY_TYPE_SATA or PHY_TYPE_USB or PHY_TYPE_DP or PHY_TYPE_SGMII","type":"text"}]},{"type":"paragraph","content":[{"text":"CONTROLLER_INSTANCE = ","type":"text"}]},{"type":"paragraph","content":[{"text":"Depends on controller type used, can be any of below mentioned ","type":"text"}]},{"type":"paragraph","content":[{"text":" PHY_TYPE_PCIE : 0 or 1 or 2 or 3","type":"text"}]},{"type":"paragraph","content":[{"text":" PHY_TYPE_SATA : 0 or 1","type":"text"}]},{"type":"paragraph","content":[{"text":" PHY_TYPE_USB : 0 or 1","type":"text"}]},{"type":"paragraph","content":[{"text":" PHY_TYPE_DP : 0 or 1","type":"text"}]},{"type":"paragraph","content":[{"text":" PHY_TYPE_SGMII: 0 or 1 or 2 or 3","type":"text"}]},{"type":"paragraph","content":[{"text":"LANE_FREQ = refclk number that has the desired frequency","type":"text"}]},{"type":"paragraph","content":[{"text":"Example:","type":"text"}]},{"type":"paragraph","content":[{"text":"PSGTR changes:","type":"text","marks":[{"type":"strong"}]}]},{"type":"codeBlock","content":[{"text":" refclk4:psgtr_dp_clock {\n compatible = \"fixed-clock\";\n #clock-cells = <0x00>;\n clock-frequency = <27000000>;\n };\n\n refclk3:psgtr_usb_clock {\n compatible = \"fixed-clock\";\n #clock-cells = <0x00>;\n clock-frequency = <26000000>;\n };\n\n refclk2:psgtr_sata_clock {\n compatible = \"fixed-clock\";\n #clock-cells = <0x00>;\n clock-frequency = <125000000>;\n };\n\n refclk1:psgtr_pcie_clock {\n compatible = \"fixed-clock\";\n #clock-cells = <0x00>;\n clock-frequency = <150000000>;\n };\n\n psgtr: phy@fd400000 {\n compatible = \"xlnx,zynqmp-psgtr-v1.1\";\n reg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>;\n reg-names = \"serdes\\0siou\";\n #clock-cells = <0x01>;\n clocks = <&refclk1 &refclk2 &refclk3 &refclk4>;\n\t\t\t\t\t\t/* ref clk instances used per lane */\n clock-names = \"ref0\\0ref1\\0ref2\\0ref3\";\n #phy-cells = <0x04>;\n status = \"okay\";\n };","type":"text"}]},{"type":"paragraph","content":[{"type":"hardBreak"}]},{"type":"paragraph","content":[{"text":"SATA instance 1 using Lane 3 refclk:125MHZ:","type":"text","marks":[{"type":"strong"}]}]},{"type":"codeBlock","content":[{"text":" ahci@fd0c0000 {\n compatible = \"ceva,ahci-1v84\";\n status = \"okay\";\n reg = <0x00 0xfd0c0000 0x00 0x2000>;\n \t\t\t\t\t.....\n /* psgtr_phandle....lane number... controller_type...instance....refclk */\n phys = <&psgtr 0x3 PHY_TYPE_SATA 0x01 0x1>;\n reset-names = \"sata_rst\";\n resets = <0x1a 0x10>;\n };","type":"text"}]},{"type":"paragraph","content":[{"text":"USB instance 0 lane 2 refclk 26MHZ:","type":"text","marks":[{"type":"strong"}]}]},{"type":"codeBlock","content":[{"text":" usb0@ff9d0000 {\n #address-cells = <0x02>;\n #size-cells = <0x02>;\n status = \"okay\";\n compatible = \"xlnx,zynqmp-dwc3\";\n reg = <0x00 0xff9d0000 0x00 0x100>;\n clock-names = \"bus_clk\\0ref_clk\";\n \t\t\t\t\t....\n resets = <0x1a 0x3b 0x1a 0x3d 0x1a 0x3f>;\n reset-names = \"usb_crst\\0usb_hibrst\\0usb_apbrst\";\n\t\t\t\t\t\t......\n dwc3@fe200000 {\n compatible = \"snps,dwc3\";\n status = \"okay\";\n reg = <0x00 0xfe200000 0x00 0x40000>;\n interrupt-parent = <0x04>;\n interrupt-names = \"dwc_usb3\\0otg\\0hiber\";\n interrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>;\n #stream-id-cells = <0x01>;\n\t\t\t\t\t\t\t\t.....\n dr_mode = \"host\";\n maximum-speed = \"super-speed\";\n \t\t phy-names = \"usb3-phy\";\n\t\t\t\t\t\t\t\t/* psgtr_phandle....lane number... controller_type...instance....refclk */\n\t\t phys = <&psgtr 0x2 PHY_TYPE_USB 0x00 0x02>;\n };\n };","type":"text"}]},{"type":"paragraph","content":[{"type":"hardBreak"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Test Procedure","type":"text"}]},{"type":"paragraph","content":[{"text":"As this driver is being used by SATA, USB, PCIe, SGMII and DP protocols. Testing the functionality of any of those protocols will automatically test this IP.","type":"text"},{"type":"hardBreak"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Expected O/P","type":"text"}]},{"type":"paragraph","content":[{"text":"Once linux is booted type \"","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"text":"grep | gtr","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}},{"type":"strong"}]},{"text":"\" and check whether PLL lock is happening, the below output is expected","type":"text","marks":[{"type":"textColor","attrs":{"color":"#333333"}}]},{"type":"hardBreak"}]},{"type":"codeBlock","content":[{"text":"root@Xilinx-ZCU102-2016_3:~# dmesg | grep gtr\n[ 6.575387] xilinx-psgtr fd400000.zynqmp_phy: Lane:3 type:3 protocol:2 pll_locked:yes\n[ 6.808627] xilinx-psgtr fd400000.zynqmp_phy: Lane:2 type:0 protocol:3 pll_locked:yes\n[ 7.570858] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:8 protocol:4 pll_locked:yes","type":"text"}]},{"type":"paragraph","content":[{"type":"hardBreak"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Mainline Status","type":"text"}]},{"type":"paragraph","content":[{"text":"The current driver available in the Xilinx Linux git is in sync with the open-source kernel.","type":"text","marks":[{"type":"textColor","attrs":{"color":"#172b4d"}}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Change log","type":"text"}]},{"type":"paragraph","content":[{"text":"2025.1","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Kernel upgrade to 6.12","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"2024.2","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"phy: xilinx: phy-zynqmp: Fix SGMII linkup failure on resume ","type":"text"},{"text":"4dd8383fcbe1","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/Xilinx/linux-xlnx/commit/4dd8383fcbe128090403515c219e477b7f1b4c89"}}]}]}]}]},{"type":"paragraph","content":[{"text":"2024.1","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Kernel upgrade to 6.6","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"2023.2","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"None","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"2023.1","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Kernel upgrade to 6.1","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Updated Comment Description- SGMII is validated on SOM KR260. ","type":"text"},{"text":"7f2f1a1","type":"text","marks":[{"type":"strong"},{"type":"link","attrs":{"href":"https://github.com/Xilinx/linux-xlnx/commit/7f2f1a1ba72d56f1733d6117b1b4b02473c977d9"}}]}]}]}]},{"type":"paragraph","content":[{"text":"2022.2","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"None","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"2022.1","type":"text","marks":[{"type":"strong"}]},{"type":"hardBreak"},{"text":"Summary:","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Kernel upgrade to 5.15 ","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Fix bus width setting for SGMII ","type":"text"},{"text":"5d691d","type":"text","marks":[{"type":"strong"},{"type":"link","attrs":{"href":"https://github.com/Xilinx/linux-xlnx/commit/5d691d8cc38fae24527b5145aa17237ba6643203"}}]}]}]}]},{"type":"paragraph","content":[{"text":"2021.2","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"None","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"2021.1","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"zynqMp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Fix unused-function compiler warning","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Handle the clock enable/disable properly","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Skip PHY initialization and PLL lock for USB","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Note: This new psgtr configuration is applicable from release Xilinx - 2021.1","type":"text","marks":[{"type":"strong"}]}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Related Links","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Linux Device Drivers","type":"text","marks":[{"type":"link","attrs":{"href":"https://xilinx-wiki.atlassian.net/wiki/display/A/Linux+Drivers"}}]}]}]}]}],"version":1}