Zynq UltraScale+ MPSoC Design Example: PL Temperature and Voltage Monitor

Requirements

  1. ZCU102 development board (This design example has been tested on silicon 4.0 rev1.0 board)
  2. SDK (2017.4 release and above)

Design Implementation

This design example initializes, configures and monitors PL on-chip temperature and various voltages from PMU Microblaze periodically. Following is the design implementation:
  1. PMU Firmware application runs on PMU Microblaze. It registers a new module for monitoring PL on-chip temperature and voltages using PSU Sysmon driver APIs.
  2. This module initializes the System Monitor device driver instance.
  3. It runs the self-test on the device.
  4. It sets up the sequence registers to continuously monitor the following channels:
    1. PL temperature (Temp_PL)
    2. PL internal voltage (VCCINT)
    3. PL auxiliary voltage (VCCAUX)
    4. ADC positive (VREFP) and negative (VREFN) reference voltages
    5. PL Block RAM voltage (VCCBRAM)
    6. LPD (VCC_PSINTLP), FPD (VCC_PSINTFP) and PS auxiliary (VCC_PSAUX) voltages
    7. PL Auxiliary voltages (VAUX{0:15}) – These channel values are valid only when they are configured in the hardware design
    8. PL User defined voltages (VUser{0:3}) – These channel values are valid only when they are configured in the hardware design
    9. PL ADC power supply voltage (VCCADC)
  5. It enables the channel sequencer in continuous sequencer cycling mode to start the sequence.
  6. And it adds a scheduler task to read the latest on-chip temperature and voltages continuously for every 10 seconds and prints on the terminal

Application creation steps

  1. Create FSBL application either for A53 or for R5 processor
  2. Create PMU Firmware application. Download this zip file ,extract and add the extracted source files to the PMU Firmware application. This creates a new custom module in PMU Firmware which initializes sysmon and monitors PL temperature and voltages periodically in continuous sequencer cycling mode. Please refer to "Custom Module Usage" section in chapter 10 in Zynq UltraScale+ MPSoC Software Developer Guide for reference
  3. Enable scheduler module by defining ENABLE_SCHEDULER macro and rebuild the PMU Firmware application

Steps to create boot image

  1. In SDK, go to Xilinx -> Create Boot Image. Create Boot Image window appears as below
    image1.png
  2. Select Zynq MP in Architecture category. Select Create new BIF file option
  3. Browse and select path for Output BIF file path
  4. Click on Add button to add partition. Select fsbl_a53 executable path at File path. Select Partition type as bootloader, Destination Device as PS and Destination CPU as A53 x64. Click OK. Please see the below image for reference
    Image2.png
  5. Click on Add button again to add BIT file partition. Select PL bit file path at File path. Select Partition type as datafile and Destination Device as PL. Click OK. Please check below image for reference
    image3.png
  6. Click on Add button to add PMU Firmware partition. Select pmu_firmware executable file path at File path. Select Partition type as datafile, Destination Device as PS and Destination CPU as PMU. Click OK. Please see the below image for reference
    image4.png
  7. Now click on Create Image. BOOT.BIN is created at Output BIF file path. Copy the BOOT.BIN to SD card and power-on ZCU102 board in SD boot mode. And observe the prints on UART terminal

Snippet of BIF file

Below is the snippet of BIF file created with the steps mentioned above
//arch = zynqmp; split = false; format = BIN
the_ROM_image:
{
        [fsbl_config]a53_x64
        [bootloader]C:\Images\fsbl_a53.elf
        [destination_device = pl]C:\Images\design_1_wrapper.bit
        [destination_cpu = pmu]C:\Images\pmu_fw.elf
}
 
Note: User need to make sure that PL design is included in the hardware to run this application successfully and also the bit file should be programmed before running the PMU application

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