Zynq UltraScale+ MPSoC RPU Lock Step Mode

The Cortex-R5 processor set to operate in the lock configuration uses only one set of CPU interfaces. Because Cortex-R5 processor only supports the static split/lock configuration, switching between these modes is only permitted while the processor group is held in power-on reset.

This page explains in detail how to run the RPU in Lock-step mode.

Creation of QSPI Standalone Boot Image for RPU Lock-Step Mode

1. Set the Petalinux environment using the following command
$source <Petalinux installation path>/settings.sh

2. Create a bif file “QSPI_R5_0.bif” with the following contents:
$cat QSPI_R5_0.bif
[fsbl_config] r5_single
[bootloader] R5_FSBL.elf
[destination_cpu=r5-0] R5_core0_hello_world.elf
3. Run the bootgen tool to generate the bin file
$ bootgen -r -w –image ./QSPI_R5_0.bif -o Boot.bin

4. Create the QEMU QSPI single mode boot image
$ dd if=/dev/zero of=qemu_qspi_R5_0.bin bs=32M count=1
1+0 records in
1+0 records out
33554432 bytes (34 MB) copied, 0.300993 s, 111 MB/s
$ dd if=Boot.bin of=qemu_qspi_R5_0.bin bs=1 seek=0 conv=notrunc
{{87448+0 records in}}
{{87448+0 records out}}
{{87448 bytes (87 kB) copied, 3.14043 s, 27.8 kB/s}}
5. Now the QEMU QSPI single mode boot image qemu_qspi_R5_0.bin can be used for the execution on QEMU

6. Execute the application on R5 in Lock-Step mode using the following command
$ qemu-system-aarch64 -nographic -M arm-generic-fdt -dtb ./xilinx-zynqmp-arm.dtb -device loader,file=R5_FSBL.elf,cpu=4 -device loader,addr=0xff5e023c,
data=0x80008fde,data-len=4 -mtdblock qemu_qspi_R5.bin -boot mode=1
Xilinx Resticted QEMU Sep 29 2014 20:00:35.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (git-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
Hello World R5 Lockstep

Related Links

Xilinx SDK User Guide
Software Development Flow