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Design Overview


This module shows how to add a Test Pattern Generator (TPG) implemented in the PL.

base-trd-2016-3-dm6-bd.png



Design Components


This module requires the following components:
  • zcu102_base_trd (Vivado)
  • pmu_fw
  • petalinux_bsp
    • zynqmp_fsbl
    • bl31
    • u-boot
    • kernel
    • device tree (system-dm6.dts)
    • rootfs
  • video_lib
  • video_qt2



Build Flow Tutorials


PL Base TRD


This tutorial shows how to build the Base TRD Vivado design that implements the TPG capture pipeline.

  • Create a Vivado project. Select 'es1' instead if you are targeting a rev D board with ES1 silicon.
    % cd $TRD_HOME/pl/zcu102_base_trd
    % vivado -s ./scripts/create_project.tcl -tclargs -platform zcu102 -silicon es2
  • Implement the design and generate a bitstream
    base-trd-2016-3-dm6-base-trd-bit.jpg
  • Copy the generated bitstream to the PetaLinux directory or alternatively use the pre-built bit file that is already bundled with the PetaLinux BSP.
    % cp -f project/zcu102_base_trd.runs/impl_1/zcu102_base_trd_wrapper.bit $TRD_HOME/apu/petalinux_bsp/images/linux

PMU Firmware


Please refer to design module 1 - PMU firmware for instructions or skip this step if you have built the PMU firmware in a previous module.

PetaLinux BSP


This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.

  • The petalinux-config step can be skipped if this was already done in a previous module.
    % cd $TRD_HOME/apu/petalinux_bsp
    % petalinux-config --get-hw-description=./hw-description --oldconfig
  • Select the device-tree matching design module 6 and build all Linux image components. If you have run petalinux-build in a previous module, the build step will be incremental.
    % cd subsystems/linux/configs/device-tree
    % cp system-dm6.dts system-top.dts
    % petalinux-build
    % cd -
  • Create a boot image.
    % cd images/linux
    % petalinux-package --boot --bif=dm6.bif --force
  • Copy the generated boot image and Linux image to the dm6 SD card directory.
    % mkdir -p $TRD_HOME/images/dm6/bin
    % cp BOOT.BIN image.ub $TRD_HOME/images/dm6
  • Copy the file autostart.sh from the pre-built dm9 SD card directory.
    % cp $TRD_HOME/images/dm9/autostart.sh $TRD_HOME/images/dm6

Video Qt Application


There is no need to rebuild the video_qt2 application if you have already built it in module 5, otherwise follow the instructions from module 5.

  • Copy the generated video_qt2 executable to the dm6 SD card directory.
    % cp -f video_qt2/video_qt2 $TRD_HOME/images/dm6/bin
  • Copy the video_qt2 wrapper scripts from the pre-built dm9 SD card directory.
    % cp $TRD_HOME/images/dm9/bin/run_video.sh $TRD_HOME/images/dm9/bin/video_qt2_wrap.sh $TRD_HOME/images/dm6/bin/



Run Flow Tutorial


  • See here for board setup instructions.
  • Copy all the files from the $TRD_HOME/images/dm6 SD card directory to a FAT formatted SD card.
  • Power on the board to boot the images; make sure INIT_B, done and all power rail LEDs are lit green.
  • After ~30 seconds, the display will turn on and the application will start automatically, targeting the max supported resolution of the monitor (one of 3840x2160 or 1920x1080 or 1280x720).
  • Upon application exit, use the below login and password to log into the framebuffer or serial console:
    root@Xilinx-ZCU102-2016_3 login: root
    password: root
  • The SD card file system is mounted at /media/card
  • To re-start the TRD application type run_video.sh
  • The user can now control the application from the GUI's control bar (bottom) displayed on the monitor.
    tpg_dm-6.jpg
  • By default, application launches with VIVID as a video-source, user can also select TPG from the "Video-source selection" button present on the GUI's control-bar.
    • Virtual Video Device (VIVID): emulates a USB webcam purely in software
    • USB Webcam (UVC): using the universal video class driver
    • Test Pattern Generator (TPG); implemented in the PL
  • The video info panel (top left) shows essential settings/statistics.
  • The CPU utilization graph (top right) shows CPU load for each of the four A53 cores.