Preliminary


Zynq UltraScale+ MPSoC Power Advantage Tool 2018.1

Now that you have installed and run the Pre-Built Power Advantage Tool, let’s take a moment to see what else you can do with it. The Power Advantage Tool Control Console can be used, with designs, to monitor power during the design process. In addition, the Power Advantage Tool can be used as a demonstration of the power savings with various designs.

Document History

Date
Version
Author
Description of Revisions
Jul 2, 2018

jerrywo
Created


1 Power Advantage Tool


Known 2018.1 Issues:
(1) The MSP430 source builds the compatible MSP430 version, but may not support all debug features.
(2) The following CRs are open against the example code for the following features: CR-1005503 FPD Off, CR-1005912 Power Off Suspend.

Note: The Power Advantage Tool now takes control of the APU serial port if available. To give user control of the APU terminal, close the Power Advantage Tool, then launch the following script to open terminals, then open the Power Advantage Tool again. The Power Advantage Tool will complain that "No APU UART available", but just close that message.

20171220_No_APU_UART.png

1.1 Launching the Power Advantage Tool Control Console

Warning: If you have connected Micro USB (UART) (J83) to PC for the first time, or switched boards, you may need to wait a few minutes for the PC to recognize the new hardware. Then you can open the Power Advantage Tool.

Launch the Power Advantage Tool Shortcut at C:\ZynqUS_Demos\ZynqusPowerTool.exe Shortcut.
In a few seconds, you should see a Power Advantage Tool Control Console window with a Power Report. The Power numbers should update every few seconds.
If it is not displayed properly, refer to “Common Setup Issues”, and debug until the “Power Advantage Tool is alive” before returning here to continue.

1.2 Getting to Know the Power Advantage Tool Control Console


After successfully launching the Power Advantage Tool, you should see the following Power Advantage Tool Control Console window (may take a few seconds):

Power Tool Console.png
Figure 1. Power Advantage Tool Control Console
This interface is important to most of the demonstrations, so it would be good to familiarize yourself with it. Take a moment to identify the following:
  • Zoom Display (transparent button [ ]) (A) resizes to fill a 1920x1080 display.
  • Close (transparent button [X]) (B)
  • Minimize (C)
  • Select (D) Selects the display mode (Rails, Plot, About contains the version number)
  • Preset (E) Places the ZCU102 into a selected state.
  • Block Diagram of Zynq (F) shows the current device state.
  • Power Totals for various domains (G) (Note: There can be a few seconds delay for measurement and update.)

Note: The Temperature is polled only every few seconds, so it appears after a short time.

Here is a Table of the Rails for ZCU102:
  • VCCPSINTFP – Core Full Power Domain
  • MGTRAVCC – GTX Power
  • MGTRAVTT – GTX Termination Power
  • VCCO_PSDDR_504 – PS DDR Controller IO
  • VCCPSDDRPLL – PS DDR PLL Power
  • VCCPSINTLP – Core Low Power Domain
  • VCCPSAUX – Aux and GPIO
  • VCCPSPLL – PS PLL Power
  • VCCOPS – PS IO Banks MIO0/1/2
  • VCCOPS3 – Dedicated PS IO
  • VCCINT – PL Operating
  • VCCBRAM – Block RAM
  • VCCAUX – Auxiliary Circuits
  • VCC1V2 – DDR Termination
  • VCC3V3 – Main PMBUS Utility Rails
  • MGTAVCC – Receiver and Transmitter Internal
  • MGTAVTT – Transmit Driver

It is a power advantage to be able to turn off unused circuitry. The more power islands and domains you have, the more flexibility you have to save power.
Islands are power switched internally to the Zynq UltraScale+ MPSoC, whereas Domains switch power rails externally to the Zynq device. When Domain switching can be done, this has the advantage of drawing no power by being able to completely turn off a portion of the silicon device.
Note: Switching off domains can clear the program memory until reboot.
Control can be over entire Domains or individual Islands. The next sections will demonstrate switching the Power Domains.

1.3 Domain Control


Power Domains are broad sections of the Zynq UltraScale+ MPSoC an d are the Full Power, Low Power, and Programmable Logic Domains.
The Power Advantage Tool requires no further setup to have access to the Power Domain Controls.

Power Domain Controls 20161005.png
Figure 2. Power Domain Controls

With the Power Advantage Tool running, identify the following controls:
(A) Preset Button
(B) Low Power Domain Button
(C) FulI Power Domain Button
(D) Four A53 Processor Core Power Island Buttons
(E) Programmable Logic Domain Button

1.4 PL Control


The demo PL design contains a configurable design.
Changing the PL design configuration allows the Power to be compared for various designs.

PL Controls.png
Figure 3. PL Controls.

PL design controls:
  • Work Utilization and Clock Rate (A): Select the PL algorithm and set standard operating parameters.
  • Options (B): Select the PL algorithm and set the non-standard operating parameters.
  • Information i (C): Display information (block diagram) of the PL algorithm. Turn off all the Power Domains (B) (C) (E)
Note: Any change to the PL design controls triggers an update, causing the PL power to rise to maximum, until all PL design controls are incrementally turned off again. The GUI currently follows the "dimmer" flow where all performance starts "on" and performance is incrementally turned off.

1.5 Selecting Displays


Pressing the Select button gives a menu to select from various displays:
  • Plot: Graphically displays the power for each of the three domains and total power.
Plot.png
Figure 4. Plot.
  • Rails: This is the default display. Rails displays the voltage and power for each of the rails, as well as the chip temperature, and the total power. The power measurements are made external to the Zynq by TI INA226 chips.
Rails.png
Figure 5. Rails.
  • Sysmon: This displays the temperature and voltages read by the System Monitor on the Zynq.
Sysmon.png
Figure 6. Sysmon.
  • Legend: This page defines each of the Zynq rails.
Legend.png
Figure 7. Legend.
  • About: This page contains the legal notice, as well as the software revisions for Qt and MSP430 code.
About.png
Figure 8. About.

1.6 Linux


This section runs the "Dimmer Demo" from the Linux command line.

Note: This portion of the demo requires a user APU terminal. The Power Advantage Tool now takes control of the APU serial port if available. To give user control of the APU terminal, close the Power Advantage Tool, then launch the following script to open terminals, then open the Power Advantage Tool again. The Power Advantage Tool will complain that "No APU UART available", but just close that message.

20171220_No_APU_UART.png

From C:\ZynqUS_Demos\2017.1_Demos, launch 00a_open_terminals_ZCU102.ahk.
Note: Additional convenience additional scripts (noted in parentheses) for the steps below are available from C:\ZynqUS_Demos\2017.1_Demos

1.6.1 Linux A53 All Busy

(01_demo_all_busy.ahk)

From Linux, we can fully load an APU core:

yes > /dev/null &

Repeating this four times fully loads all APU cores.
This can be verified by running "top" command.

1.6.2 Linux A53 CPU Hotplug

(02_demo_3_off.ahk)

The user may take one or more APU cores on-line and off-line as needed.

Keep one CPU core busy with
yes > /dev/null &
top (Control-C exits top)
Top indicates that the A53 is 25% busy.
Note the change in power.

Fill the remaining CPU cores with
yes > /dev/null &
yes > /dev/null &
yes > /dev/null &
top
Note the change in power.
Note that top reports were 100% busy

Take cpu3 offline with
echo 0 > /sys/devices/system/cpu/cpu3/online
Note the change in power

Repeat this two more times
echo 0 > /sys/devices/system/cpu/cpu2/online
echo 0 > /sys/devices/system/cpu/cpu1/online
top
And note the change in power
But also note that top thinks were still 100% busy (of the cores in the system)

Try one more time
echo 0 > /sys/devices/system/cpu/cpu0/online
cat /sys/devices/system/cpu/cpu0/online
top
There's no change in power
The core still thinks its on
And we're still 100% busy (the PMU does not allow us to turn off all the CPU cores this way)

Turn the cores back on again and finally remove the tasks keeping the cores busy
echo 1 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu2/online
echo 1 > /sys/devices/system/cpu/cpu3/online
top
killall yes
top

For more on the Linux CPU Hotplug API, please refer to
Zync UltraScale+ MPSoC Power Management - Linux Kernel

1.6.3 Linux A53 Frequency Scaling

(03_demo_3_off_299mhz.ahk, requires 02_demo_3_off.ahk first)

The user may change the frequency of an APU core as needed.

Take note of the power
Then change the frequency of an A53 core to 299MHz
echo 299999 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
Note the change in power.

Change the frequency of the A53 core back to 1200MHz
echo 1200000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed

For more on the Linux Frequency Scaling API, please refer to
Zync UltraScale+ MPSoC Power Management - Linux Kernel

1.6.4 Linux A53 Power On Suspend to RAM

(04_demo_a53_suspend_uart.ahk)

From Linux, we can Suspend, but first we program a wake source.

To suspend and wake from UART:
echo enabled > /sys/devices/platform/amba/ff000000.serial/tty/ttyPS0/power/wakeup
echo mem > /sys/power/state
Note the drop in power ... Then press a key to resume.

To suspend and wake from a timer:

echo +30 > /sys/class/rtc/rtc0/wakealarm
echo mem > /sys/power/state
Note the drop in power ... Then 30 seconds later, we resume.

For more on the Linux Suspend API, please refer to
Zync UltraScale+ MPSoC Power Management - Linux Kernel

1.6.5 Linux A53 FPD Off Suspend to RAM

(05_demo_rpu_off.ahk, then 04_demo_a53_suspend_uart.ahk)

From Linux, we can demonstrate FPD Off Suspend to RAM by first turning off RPU:

echo request_wakeup 8 1 0 1 > /sys/kernel/debug/zynqmp_pm/power
echo force_powerdown 6 > /sys/kernel/debug/zynqmp_pm/power

Then by running the commands in the previous section to A53 Suspend to RAM

Note: It is technically possible to have the FPD Off while RPU is still running (not using anything in FPD). We hope to show that mode in a future version of the Power Advantage Tool Demo.

Caution: The FPD Off Suspend to RAM feature is currently available on a limited basis. Please see your Field Application Engineering representative for more information on this feature.

Caution: For reliable RAM retention, this feature requires the latest MSP430 code, or for PSDDR VCCO SEL jumper J56 to be moved from pins 1,2 (default) to pins 3,4 to keep the DDR I/O Rail powered.

1.6.6 Linux A53 Debugfs

Warning: This API is for debug, and is likely cause unexpected problems with normal Power Management.

Here's an example of the format:
echo request_node 22 1 100 1 > /sys/kernel/debug/zynqmp_pm/power
Node 22 = USB_0
Capabilities 1 = Preserve context
QoS 100 = Quality of Service max
Ack 1 = Blocking acknowledge requested

For more on the Linux Debugfs API, please refer to XPm_RequestNode
Zync UltraScale+ MPSoC Power Management - Linux Kernel
Power Management Framework User Guide: For Zynq UltraScale+ MPSoC Devices UG1199

1.7 GUI


(Demo from the GUI is not supported in this version.)

1.8 Telnet


(Telnet is not supported in this version.)

1.9 Ubuntu


(This version is PetaLinux only, Ubuntu is not supported in this version.)

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