Zynq UltraScale+ MPSoC Power Advantage Tool 2017.3 part 4 - Building and Running the PL Design From Sources
[Preliminary]

Every customer design will have its own PL code. Power readings can be demonstrated simply by building the customer PL design into the Power Advantage Tool. Additional features can be gotten by combining the customer design with the Power Advantage Tool PL sources. This section describes how to build and run the Power Advantage Tool PL design from sources.

1 PL Design

1.1 Building the PL Design

The steps to rebuild the PL design from sources are as follows:
  • Install the Vivado Tools as described here.
  • Windows > All Programs > Xilinx Design Tools > Vivado 2017.3 > Vivado 2017.3 > File > Open Project > File name: C:\zynqus\pwr\hw\zcu102_ecc\zcu102.xpr > OK
  • Tcl Console > get_board_parts
  • Program and Debug (at bottom of menu) > Generate Bitstream
  • Note: If you modify the PL design and need to export a new psu_init.tcl file, prior to 2016.4, you will need to manually modify it to support the DisplayPort feature. This can be done by copying C:\zynqus\pwr\sw\zu_processor_gpio_wrapper_hw_platform_0\location\psu_init.tcl to C:\zynqus\pwr\sw\psu_init_new.tcl, and commenting out the line "mask_poll 0xFD4023E4 0x00000010". If you do not, the SDK R5 debugger will not run.

1.2 Running the PL Design from the JTAG Debugger

The steps to run the PL design from the JTAG debugger are as follows:
  • Set Mode SW6 to On-On-On-On, and power cycle the ZCU102 board.
  • After Building the PL Design: Program and Debug > Open Hardware Manager > No hardware target is open. Open target > Auto Connect > There are no debug cores. Program device > xczu9eg_0 > Program

1.3 Running the PL Design from SD Image

The steps to run the PL design from SD Image are as follows:
  • After Building the PL Design in 1.1, Build the SD card and run as described here.

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