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ISE DS 14.4 Targeted Base Reference Design
ISE DS 14.3 Targeted Base Reference Design
ISE DS 14.2 Targeted Base Reference Design
ISE DS 14.1 Targeted Base Reference Design

1 Introduction


This page provides instructions on how to build various components of the Zynq Base Targeted Reference Design (TRD) and how to setup the hardware platform and run the design on the ZC702 Evaluation Kit. The ZC702 Evaluation kit is based on a XC7Z020 CLG484-1 Zynq-7000 All Programmable SoC (AP SoC) device. For additional information, refer to Zynq-7000 All Programmable SoC: ZC702 Evaluation Kit and Video and Imaging Kit Getting Started Guide.

1.1 About the Base TRD

The Base TRD is an embedded video processing application designed to showcase various features and capabilities of the Zynq Z-7020 AP SoC device for the embedded domain. The Base TRD consists of two elements: The Zynq-7000 AP SoC Processing System (PS) and a video processing pipeline implemented in Programmable Logic (PL). The AP SoC allows the user to implement a video processing algorithm that performs edge detection on an image (Sobel filter) either as a software program running on the Zynq-7000 AP SoC based PS or as a hardware accelerator inside the AP SoC based PL. The Base TRD demonstrates how the user can seamlessly switch between a software or a hardware implementation and evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications. For additional information, please refer to UG925: Zynq-7000 All Programmable SoC: ZC702 Base Targeted Reference Design User Guide.

1.2 Download the TRD

An archive with the TRD files can be downloaded here (requires to sign up).

1.3 Base TRD Package Contents

The Zynq Base TRD package is released with the source code, Xilinx PlanAhead and SDK projects, and an SD card image that enables the user to run the video demonstration and software application. It also includes the binaries necessary to configure and boot the Zynq-7000 AP SoC board. This wiki page assumes the user has already downloaded the Base TRD package and extracted its contents to the Base TRD home directory referred to as ZYNQ_TRD_HOME in this wiki.





zc702-zvik-base-trd-rdf0286-dir-structure.png




2 Prerequisites

Note: The provided logiCVC evaluation IP core has a 1 hour timeout built-in such that the display freezes after the timer expires. The pre-built bitfile and boot images are built from a full logiCVC IP core and don't expire.

3 Building the FPGA Hardware Bitstream


This section explains how to generate the FPGA hardware bitstream using the Xilinx PlanAhead tool and how to export the hardware platform to Xilinx Software Development Kit (SDK) for software application development. Inside the PlanAhead project, a Xilinx Platform Studio (XPS) project is referenced that contains the actual hardware design.

3.1 Building the Bitstream


A pre-compiled bitstream can be found at $ZYNQ_TRD_HOME/boot_image/system.bit.

Steps for building the FPGA hardware bitstream

Launch PlanAhead:
  • On Windows 7, select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.5 > PlanAhead >PlanAhead.
  • On Linux, enter planAhead at the command prompt.

From the PlanAhead welcome screen, click Open Project from the Getting Started group.

pa_build_01.jpg
Open the PlanAhead project provided in the package. Click Browse and navigate to the $ZYNQ_TRD_HOME/hw/pa_proj project folder, select zynq_base_trd.ppr in the Open Project window, and press OK.

14.3_planahead02.jpg

In the Flow Navigator pane on the left-hand side under Program and Debug, click Generate Bitstream. The bitstream will be generated at $ZYNQ_TRD_HOME/hw/pa_proj/zynq_base_trd.runs/impl_1/system_stub.bit.

14.3_planahead01.png
Note: A message window will pop up, saying there are few critical warning messages. Ignore these warnings and press OK to continue with the bitstream generation.


3.2 Exporting the Hardware Platform to SDK

A pre-generated hardware platform project can be found at $ZYNQ_TRD_HOME/sw/hw_platform.
Steps for exporting the hardware platform to SDK
.14.3_planahead03.png
From the PlanAhead menu bar, select File > Export > Export Hardware for SDK

In the Export Hardware window press OK. The SDK hardware platform will be exported to $ZYNQ_TRD_HOME/hw/pa_proj/zynq_base_trd.sdk/SDK/SDK_Export.
14.3_planahead04.png

Note: If the Launch SDK option is checked in the Export Hardware window, SDK will be launched immediately after SDK export has completed. This is not recommended at this point.


4 Building the First Stage Boot Loader (FSBL)


This section explains how to import and build the First Stage Boot Loader (FSBL) and the standalone OS based Board Support Package(BSP) from the provided SDK projects. A pre-compiled FSBL executable can be found at $ZYNQ_TRD_HOME/boot_image/zynq_fsbl.elf.

Note: The provided FSBL project is a customized version of the FSBL SDK project template. The following features have been added to the Base TRD version:
  • Added I2C FMC detection sequence
  • Added I2C initialization sequence for HDMI receiver (ADV7611) on Avnet IMAGEON FMC


Steps for building the FSBL

Launch Xilinx SDK:
  • On Windows 7, select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.5 > EDK > Xilinx Software Development Kit.
  • On Linux, enter xsdk at the command prompt.

In the Workspace Launcher window, click Browse and navigate to $ZYNQ_TRD_HOME/sw, then click OK. Close the welcome screen.

TRD14.5_Workspace.png

To import the hardware platform (hw_platform) and FSBL (zynq_fsbl) SDK projects into the SDK workspace, select File > Import.


fsbl_build_03.jpg

Note: The zynq_fsbl project requires a hardware platform SDK project generated by SDK export. Instead of the provided hw_platform project, the one generated in Section 3.2 can be used. This requires the user to update the project reference of the zynq_fsbl project. It is not recommended at this point.

In the Import wizard, expand the General folder, select Existing Projects into Workspace, and click Next.

fsbl_build_04.jpg


All projects are located at the top-level inside your SDK workspace. Click Browse and navigate to $ZYNQ_TRD_HOME/sw. Press OK.

TRD14.5_Import_Projects_01.png

Make sure the hw_platform, zynq_fsbl and zynq_fsbl_bsp projects are checked and uncheck the sobel_cmd , sobel_lib and sobel_qt projects for now. Press Finish.

TRD14.5_Import_Projects_02.png



The build process will start automatically and builds the BSP first and then the FSBL. The generated Zynq FSBL executable can be found at $ZYNQ_TRD_HOME/sw/zynq_fsbl/Debug/zynq_fsbl.elf.
This option can be changed by unchecking Project > Build Automatically from the menu bar.


TRD14.5_Build_automatically.png

To manually build the project, right click zynq_fsbl in the Project Explorer and select Build Project; to clean the project, select Clean Project.
TRD14.5_Building_FSBL.png

Note : Zynq FSBL executable is generated under zynq_fsbl/Debug directory.

5 Building the U-boot Boot Loader


This section explains how to download the sources, configure, and build the U-boot boot loader for the Zynq Base TRD. A pre-compiled U-boot executable can be found at $ZYNQ_TRD_HOME/boot_image/u-boot.elf. For additional information, refer to the Xilinx Zynq U-boot. This step requires a Linux development PC with the ARM GNU tools and Git installed (see Section 2).

Steps for building the U-boot boot loader

Set the CROSS_COMPILE environment variable and add it to your PATH.
bash> export CROSS_COMPILE=arm-xilinx-linux-gnueabi-
bash> export PATH=/path/to/cross/compiler/bin:$PATH

Clone the latest Zynq U-boot git repository from the Xilinx git server.
bash> cd $ZYNQ_TRD_HOME
bash> git clone git://github.com/Xilinx/u-boot-xlnx.git

Create a new branch named zynq_base_trd_14_5 based on the xilinx-v14.5.01 tag.
bash> cd $ZYNQ_TRD_HOME/u-boot-xlnx
bash> git checkout -b zynq_base_trd_14_5 xilinx-v14.5.01

Configure U-boot for the Zynq ZC702 Base TRD.
bash> make ARCH=arm zynq_zc70x_config

Build the U-boot boot loader. The generated U-boot executable can be found at $ZYNQ_TRD_HOME/u-boot-xlnx/u-boot.
bash> make ARCH=arm

Rename this executable to u-boot.elf. This elf is used for generating BOOT image.
bash> mv u-boot u-boot.elf

Note: The make command above also builts other tools with u-boot in u-boot-xlnx/tools directory. Such tool (for e.g mkimage) can be used later (for e.g. building uramdisk / uImage).


6 Building the Boot Image


This section explains how to create a boot image BOOT.bin from pre-compiled binaries provided in this package. The pre-compiled binaries are located at $ZYNQ_TRD_HOME/boot_image and include zynq_fsbl.elf, system.bit, and u-boot.elf. Alternatively, the user can use the generated files from Sections 3.1, 4, and 5. A pre-generated boot image can be found at $ZYNQ_TRD_HOME/sd_image/BOOT.bin.

Steps for building the boot image

Launch Xilinx SDK:
  • On Windows 7, select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.5 > EDK > Xilinx Software Development Kit.
  • On Linux, enter xsdk at the command prompt.

In the Workspace Launcher window, click Browse and navigate to $ZYNQ_TRD_HOME/sw, then click OK.

TRD14.5_Workspace.png

Select Xilinx Tools > Create Boot Image from the menu bar.

CreateZYNQBootImage.jpg


In the Create Zynq Boot Image dialog box, click on browse to add zynq_fsbl.elf and add option for system.bitand u-boot.elf files from the $ZYNQ_TRD_HOME/boot_image directory and enter or browse to $ZYNQ_TRD_HOME/boot_image in the output folder field as shown in the figure. Press Create Image. This step will generate a file named u-boot.bin, rename this to BOOT.bin .

TRD14.5_Create_Zynq_Boot_image.png

Notes:
  • Occasionally, an internal error message pops up which can be safely ignored.
  • Rename boot image u-boot.bin to BOOT.bin so that the FSBL executable can find it.
  • The order in which you add the files matters: it has to be FSBL first, then bitstream, then u-boot.

7 Building the Linux Kernel


This section explains how to download the sources, configure, patch, and build the Linux kernel for the Zynq Base TRD. It also explains how to compile a device tree. For additional information, refer to the Xilinx Zynq Linux wiki. This step requires a Linux development PC with the ARM GNU tools and Git installed (see Section 3 2).

7.1 Building the Linux Kernel Image

A pre-compiled Linux kernel can be found at $ZYNQ_TRD_HOME/sd_image/uImage.
Steps for building the Linux kernel.

Set the CROSS_COMPILE environment variable and add it to your PATH.
bash> export CROSS_COMPILE=arm-xilinx-linux-gnueabi-
bash> export PATH=/path/to/cross/compiler/bin:$PATH
Linux kernel compilation internally uses mkimage command for creating uImage (Linux Kernel Image). Hence path for mkimage command should also be added in PATH environment variable as shown below. One can use the mkimage command that is built during u-boot building process (Section 5).

bash> export PATH=$ZYNQ_TRD_HOME/u-boot-xlnx/tools:$PATH

Clone the latest Zynq Linux kernel git repository from the Xilinx git server.
bash> cd $ZYNQ_TRD_HOME
bash> git clone git://github.com/Xilinx/linux-xlnx.git

Create a new branch named zynq_base_trd_14_5 based on the xilinx-14.5-build-trd tag.

bash> cd $ZYNQ_TRD_HOME/linux-xlnx
bash> git checkout -b zynq_base_trd_14_5 xilinx-14.5-build-trd

Apply the Base TRD specific patch on top of the xilinx-14.5-build-trd tag. The patch includes:
  • Mouse sensitivity patch (As default mouse sensitivity on embedded QT GUI is quite fast)
bash> cp $ZYNQ_TRD_HOME/patches/zynq_base_trd_14_5.patch . // copy the 14.5 TRD patch from package to dev PC
bash> git apply --stat zynq_base_trd_14_5.patch // display contents of patch
bash> git apply --check zynq_base_trd_14_5.patch // check if patch can be applied
bash> git am zynq_base_trd_14_5.patch // apply the patch

Configure the Linux kernel for the Zynq ZC702 Base TRD.
bash> make ARCH=arm xilinx_zynq_base_trd_defconfig

Build the Linux kernel. The generated kernel image can be found at $ZYNQ_TRD_HOME/linux-xlnx/arch/arm/boot/uImage.
bash> make ARCH=arm uImage modules UIMAGE_LOADADDR=0x8000

7.2 Building the Linux Device Tree Blob


This step requires that the steps in Section 7.1 are completed first. A pre-compiled Device Tree Blob can be found at $ZYNQ_TRD_HOME/sd_image/devicetree.dtb.

Steps for building the Linux device tree blob

Compile the Base TRD device tree file. The output of this step is a device tree blob and can be found at $ZYNQ_TRD_HOME/linux-xlnx/devicetree.dtb.
bash> ./scripts/dtc/dtc -I dts -O dtb -o devicetree.dtb ./arch/arm/boot/dts/zynq-zc702-base-trd.dts

8 Modifying the Root File System


NOTE: Provided instructions on the wiki will not re-create the ramdisk delivered with this design.
It is recommended to use pre-built ramdisk image.

For instructions on how to modify existing ramdisk image, please refer to Xilinx Zynq Root File System Creation .

A pre-built ramdisk image is available at $ZYNQ_TRD_HOME/sd_image/uramdisk.image.gz.

Note: At the end of the etc/init.d/rcS script, a hook was added to execute a customized user script named init.sh. Our implementation of this script is located at $ZYNQ_TRD_HOME/sd_image/init.sh and takes care of the following Base TRD specific initialization:
  • mount the cross-compiled Qt/Qwt libraries image file (located at $ZYNQ_TRD_HOME/sd_image/qt_lib.img)
  • create Xilinx VDMA device node
  • auto-start the Qt GUI based video application on boot-up

One can modify this init.sh to change the system behaviour after boot up.
For example, to avoid automatic start of QT application:
  • Remove (or comment out) the line "./run_sobel.sh -qt" from the file $ZYNQ_TRD_HOME/sd_image/init.sh

9 Building the Video Software Application(s)


The Base TRD consists of two Sobel imaging filter based video applications which differ in their user interface:

  • sobel_lib : Common API for both sobel command line and GUI application. Implemented as a static library which is used by sobel_cmd and sobel_qt application projects.
  • sobel_cmd: Command line based menu where the user navigates the menu by typing into the UART terminal.
  • sobel_qt: Graphical user interface (GUI) implemented using Qt libraries and the user navigates around the application with USB keyboard and mouse.

The following three sections explain how to import and build each of the aforementioned video applications. The user should choose the design that is most suitable for his/her purposes.

9.1 Building the sobel common Library.

Steps for building the sobel common library .

Launch Xilinx SDK:
  • On Windows 7, select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.5 > EDK > Xilinx Software Development Kit.
  • On Linux, enter xsdk at the command prompt.

In the Workspace Launcher window, click Browse and navigate to $ZYNQ_TRD_HOME/sw, then click OK.

TRD14.5_Workspace.png

Note: In this tutorial, we are using the same SDK workspace as in Section 4. Hence the project explorer view will be pre-populated with the hw_platform , zynq_fsbl and zynq_fsbl_bspSDK projects. However, the current project does not require any of these projects, it is completely self-contained.


TRD14.5_Build_FSBL.png

To import the sobel_lib SDK project into the SDK workspace, select File > Import.

fsbl_build_03.jpg

In the Import wizard, expand the General folder, select Existing Projects into Workspace, and click Next.

fsbl_build_04.jpg


All projects are located at the top-level inside your SDK workspace. Click Browse and navigate to $ZYNQ_TRD_HOME/sw. Press OK.


TRD14.5_Import_Projects_01.png

Make sure the sobel_lib project is checked and uncheck the sobel_cmd and sobel_qt project for now. The hw_platform , zynq_fsbl and zynq_fsbl_bsp projects will be grayed out since they have been added to your workspace already.
Press Finish.

TRD14.5_Import_Projects_03.png


The build process will start automatically and the generated sobel_lib library can be found at $ZYNQ_TRD_HOME/sw/sobel_lib/Debug/libsobel_lib.a.This option can be changed by
unchecking Project > Build Automatically from the menu bar.
fsbl_build_08.jpg


To manually build the project, right click sobel_lib in the Project Explorer and select Build Project , to clean the project select Clean Project.

TRD14.5_building_sobel_lib.png

Note: After building sobel_lib static library project libsobel_lib.a is generated under sobel_lib/Debug directory.

9.2 Building the sobel command line interface Linux application.


A pre-compiled sobel_cmd executable can be found at $ZYNQ_TRD_HOME/sd_image/sobel_cmd.

Steps for building the command line based application

Note : Step 9.1 is mandatory before building the sobel command line interface linux application.

To import the sobel_cmd SDK project into the SDK workspace, select File > Import.

fsbl_build_03.jpg


In the Import wizard, expand the General folder, select Existing Projects into Workspace, and click Next.

fsbl_build_04.jpg


All projects are located at the top-level inside your SDK workspace. Click Browse and navigate to $ZYNQ_TRD_HOME/sw. Press OK.
TRD14.5_Import_Projects_01.png


Make sure the sobel_cmd project is checked and uncheck the sobel_qt project for now. The hw_platform ,sobel_lib, zynq_fsbl and zynq_fsbl_bsp projects will be grayed out since they have been added to your workspace already. Press Finish.


TRD14.5_Import_Projects_sobel_cmd_01.png

The build process will start automatically and the generated sobel_cmd executable can be found at $ZYNQ_TRD_HOME/sw/sobel_cmd/Debug/sobel_cmd.elf.
This option can be changed by unchecking Project > Build Automatically from the menu bar.
fsbl_build_08.jpg


To manually build the project, right click sobel_cmd in the Project Explorer and select Build Project; to clean the project, select Clean Project.
TRD14.5_building_sobel_cmd.png


Note: After building sobel_cmd application project rename sobel_cmd.elf to sobel_cmd .

9.3 Building the sobel Qt GUI Linux application.


A pre-compiled sobel_qt executable can be found at $ZYNQ_TRD_HOME/sd_image/sobel_qt.

Steps for building the Qt GUI based application

Note : Step 9.1 is mandatory before building the sobel QT GUI Linux application.

For building this project, the user is required to cross-compile the Qt and Qwt libraries for the Zynq platform. This step requires a Linux development PC with the ARM GNU tools installed (see Section 2). For detailed instructions on how to build these libraries, refer to Xilinx Zynq Qt/Qwt Libraries - Build Instructions.
Set the ZYNQ_QT_INSTALL environment variable.
export ZYNQ_QT_INSTALL=/path/to/qt/install
Note: Some of the generated Qt utilities required to build the application are specific to your host platform. Hence, you have to recompile if you intend to use a different host.

Launch Xilinx SDK:
  • On Windows 7, select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.5 > EDK > Xilinx Software Development Kit.
  • On Linux, enter xsdk at the command prompt.

In the Workspace Launcher window, click Browse and navigate to $ZYNQ_TRD_HOME/sw, then click OK.


TRD14.5_Workspace.png

Note: In this tutorial, we are using the same SDK workspace as in Section 4. Hence the project explorer view will be pre-populated with the hw_platform, sobel_lib, zynq_fsbl, and if you have completed Section 9.2 previously then sobel_cmd SDK project. However, the current project requires the Qt/Qwt libraries cross-compiled for the Zynq architecture on your host system.
TRD14.5_Build_sobel_cmd.png

To import the Qt GUI based SDK project (sobel_qt) into the SDK workspace, select File > Import.
fsbl_build_03.jpg

In the Import wizard, expand the General folder, select Existing Projects into Workspace, and click Next.
fsbl_build_04.jpg

All projects are located at the top-level inside your SDK workspace. Click Browse and navigate to $ZYNQ_TRD_HOME/sw. Press OK.
TRD14.5_Import_Projects_01.png


Make sure the sobel_qt project is checked. SDK projects including hw_platform, sobel_lib , zynq_fsbl and zynq_fsbl_bsp, and if you have completed Section 9.2 previously the sobel_cmd project will be grayed out since they have been added to your workspace already. Press Finish.
TRD14.5_Import_Projects_sobel_qt.png

For this project, please uncheck the Project > Build Automatically option from the menu bar, otherwise you will receive an error message on the automatic build (see next step).
fsbl_build_08.jpg


To manually build the project, right click sobel_qt in the Project Explorer and select Build Project; to clean the project, select Clean Project. The generated sobel_qt executable can be found at $ZYNQ_TRD_HOME/sw/sobel_qt/sobel_qt.

TRD14.5_building_sobel_qt.png

10 Running Video Demo Applications


This section explains through step by step instructions how to bring up the ZC702 board for video demonstration part of the TRD and running different video demonstrations out of the box.

The ZC702 Evaluation Kit comes with an SD-MMC card pre-loaded with binaries that enable the user to run the video demonstration and software applications. It also includes the binaries necessary to configure and boot the Zynq-7000 AP SoC based ZC-702 board.

Note: If the evaluation kit design files were downloaded online, copy the entire folder ZYNQ_TRD_HOME/sd_image from the package onto the primary partition of the SD-MMC card (which is formatted as FAT32) using a SD-MMC card reader.

10.1 Hardware Setup Requirements


The ZC702 board setup to run & test the video demonstration applications require the following items:

Requirements for TRD Linux application demo setup

  • The ZC702 evaluation board with the XC7Z020 CLG484-1 part
  • AC power adapter (12 VDC)
  • An USB Type-A to USB Mini-B cable (for UART communications) and a Tera Term Pro (or similar) UART terminal program.
  • USB-UART drivers from Silicon Labs
  • A HDMI cable.
  • FMC (FPGA Mezzanine Card).
  • External Video Source i.e. Roku HD Streaming player.
  • A SD-MMC flash card containing TRD binaries formatted with FAT32. The SD-MMC is pre-loaded with required binaries in its first partition. The pre-loaded binaries include :
    • BOOT.bin
    • devicetree.dtb
    • uImage
    • uramdisk.image.gz
    • qt_lib.img
    • init.sh
    • run_sobel.sh
    • sobel_cmd
    • sobel_qt
    • zynq-zc702-base-trd.dts
  • An USB Micro-B to female Adaptor with USB hub is needed for connecting a keyboard and a mouse.
  • An USB mouse and keyboard.
  • A display monitor that supports HD resolutions: 1920 x 1080p @ 60 Hz, and 1280 x 720 @ 60 Hz(if the user also want to validate TRD with 720p video output)

Note:The example mentioned in this package has been tested with a Asus VS228 display monitor. However, the examples should work well with any HDMI-compatible output device provided
it supports 720/1080p resolution in EDID information.
.
10.2 Board Setup

This section explains how to setup the ZC702 board to run and test video demonstration applications.

Steps for setting the board

Connect the cables as shown in Figure below to prepare the ZC702 board to run the TRD video demo applications.
zc702_zvik_setup.jpg

  • Connect a display monitor to the HDMI out port of the ZC702 board using a HDMI cable.
  • Connect a keyboard and mouse to an USB hub, which is connected to the ZC702 board Micro-B USB connector.
  • Connect an USB Mini-B cable into the Mini USB port J17 labeled USB UART on the ZC702 board and the USB Type-A cable end into an open USB port on the host PC for UART communications.
  • Connect the power supply to the ZC702 board. Do not switch the power on.

Insert a SD-MMC memory card, which contains the TRD binaries, into the SD slot on the ZC702 board.

Make sure the switches are set as shown in figure below, which allows the ZC702 board to boot from the SD-MMC card.
ug926_c3_03_061712.jpg

The ZC702 rev.C version boards does not have switches, which contains the jumpers. Use the following jumper settings: J21: 2-3, J20: 2-3, J22: 1-2, J25: 1-2, J26: 2-3

Make sure the monitor is set for HDMI or DVI 1920x1080 resolution.

10.3 Running the Qt GUI Application in 1080p mode.


A Linux application with Qt-based GUI is provided with the package. This application provides options to user for using GUI with the help of a mouse & keyboard to exercise different modes of the video demonstration.

Note: The default Linux device tree binary file devicetree.dtb configures the video output resolution to 1080p @60Hz.

After setting the board as explained in Section10.2, running the Qt-Based GUI application is explained in this section.

Steps for running the Qt-based GUI application demo

Configure the display monitor resolution to 1080p resolution: 1920 x 1080p @ 60Hz

Power on the ZC702 board.

Wait for the ZC702 board to be configured and booted with Linux. After approximately 2 minutes, a XILINX ZYNQ banner displays on the monitor, as shown in the figure.
UG926_c3_04_061212.jpg

The Qt-based video demonstration application starts. The GUI application shows up at the bottom of the display monitor.

TRD14.5_QTGui.png

The Qt-based application allows the user to experience the different use-cases build into the video demonstration and is controlled through the mouse.
The Qt application can be used in minimize / maximize mode. Transparency slider is provided to control the GUI transparency.
End user can configure sobel controls i.e. Set sobel in invert/non-invert mode and control sobel sensitivity using sensitivity slider on QT GUI.

The user can click Help for short messages and information about the control window of the QT application.

Click Enable Video to start the internal test pattern generator which displays on the display monitor.

Exercise different options by pressing the buttons available in the GUI to evaluate the different use cases mentioned in following Table.
Use Case
TPG Control
Sobel Filter Control
1
TPG Pattern
Sobel OFF
2
TPG Pattern
Sobel - SW
3
TPG Pattern
Sobel - HW
Additional Options with External Video source
4
External video
Sobel OFF
5
External video
Sobel - SW
3
External video
Sobel - HW
Video source control modes are explained as follows:
  • TPG interference
  • The input video is generated by the TPG IP implemented in the PL.
  • External video (available with the optional ZVIK FMC module)
  • The input video is supplied by an external video source and is connected through an Avnet FMC-IMAGEON card.

Sobel Filter modes are explained as follows:
  • Sobel OFF
  • No processing done. Sobel filter is bypassed.
  • Sobel – SW
  • Video processing (edge-detection filter) done by software code running on the PS.
  • Observe CPU utilization going up to 100% for one of the two CPUs (this can be seen in the CPU usage graph). In this mode, the frame rate of the video also drops to about 10 fps.
  • Sobel – HW
  • Video processing (edge-detection filtering) done by PL.
  • Observe CPU utilization going down (to approximately 0) and the frame rate jumping to 60 fps.

The video frame generated by the TPG, i.e. case 1 vs. case 2 or 3 of Table, the video frame after its object edges are found using Sobel filter algorithm is:
TRD14.5_Sobel_Algorithm.png

While exercising the modes described above, one can observe AXI bus bandwidth utilization and CPU utilization on the graphs in the Qt GUI application.

Click Exit button on the GUI using the mouse to quit the application and return the user to Linux console.

The application can be restarted by typing the following at the Linux command prompt:
zynq> cd /mnt
zynq> ./run_sobel.sh –qt
 

10.4 Running the Qt GUI Application in 720p mode.


Prerequisite:
Monitor supporting 720p mode , as current design has a strict check for supported resolution.
For more information refer to Appendix 12.2 EDID section.

Command line resolution switch utility is added to dynamically change the resolution .
To use this feature application has to be started using -res option followed by input resolution.

Steps for Running QT based GUI in 720p mode.
a) Follow similar steps as mentioned in 10.3 subsection.
b) Exit QT application by clicking on Exit button.
c) Type these commands at the Linux command prompt into the host PC based terminal:

zynq> cd /mnt
zynq> ./run_sobel.sh –qt -res 1280x720

10.5 Running the UART Menu Application in 1080p mode.


A Linux application with command line menu is also provided with the package. This application provides options to the user to exercise different modes of the video demonstration over UART communications.

Note: The default Linux device tree binary file devicetree.dtb configures the video output resolution to 1080p @60Hz..

After setting the board as explained in Section 10.2, running the UART menu based application is explained in this section.

Steps for running the UART Menu-Based application demo

Power on the ZC702 board.

Configure the display monitor resolution to either 1080p resolution: 1920 x 1080p @ 60Hz or 720p60 resolution: 1280 x 720p @60 Hz.

Start the installed UART terminal program on your host PC (e.g., Tera Term on a Windows PC, GtkTerm on a Linux PC).

Use the following UART configuration: Baud rate = 115200, bits = 8, parity = none, and stop bits = 1.
Note: This step is required to view debug information or to run the UART Menu-Based Demonstration application.

Wait for the ZC702 board to be configured and booted with Linux. After approximately 2 minutes, a XILINX ZYNQ banner displays on the monitor, as shown in the figure.
UG926_c3_04_061212.jpg

The Qt-based video demonstration application starts. The GUI application shows up at the bottom of the display monitor.
TRD14.5_QTGui.png

Click Exit button on the GUI using the mouse to quit the application and return the user to Linux console.

Go to the UART terminal started on the host PC.

Type these commands at the Linux command prompt into the host PC based UART terminal:
zynq> cd /mnt
zynq> ./run_sobel.sh –cmd
The menu-based video application demonstration starts as shown in the Figure:
UG926_c3_07_061212.jpg

Exercise different options by entering the use case number displayed in the below Table against Enter your choice : on the terminal.
Choice
TPG Control
Sobel Filter Control
1
TPG Pattern
Sobel OFF
2
TPG Pattern
Sobel - SW
3
TPG Pattern
Sobel - HW
Additional Options with External Video source
4
External video
Sobel OFF
5
External video
Sobel - SW
3
External video
Sobel - HW
Video source control modes are explained as follows:
  • TPG interference
  • The input video is generated by the TPG IP implemented in the PL.
  • External video (available with the optional ZVIK FMC module)
  • The input video is supplied by an external video source and is connected through an Avnet FMC-IMAGEON card.

Sobel Filter Modes are explained below:
  • Sobel OFF
  • No processing done. Sobel filter is bypassed.
  • Sobel – SW
  • Video processing (edge-detection filter) done by software code running on PS
  • Sobel – HW
  • Video processing (edge-detection filter) done by PL

The video frame generated by the TPG, i.e. case 1 vs. case 2 or 3 of Table, the video frame after its object edges are found using Sobel filter algorithm is:
TRD14.5_Sobel_Algorithm.png

Enter 0 to exit the application and return to the command prompt.

10.6 Running the UART Menu Application in 720p mode


Prerequisite: Monitor supporting 720p mode as current design has a strict check for supported resolution.
For more information refer to Appendix 12.2 EDID section.

Command line resolution switch utility is added to dynamically change the resolution .
To use this feature application has to be started using -res option followed by input resolution.

Steps for Running UART Menu based Demonstration Application in 720p mode.
a) Follow similar steps as mentioned in 10.5 subsection.
b) Exit UART application [enter 0 to exit ].
c)Type these commands at the Linux command prompt into the host PC based terminal:

zynq> cd /mnt
zynq> ./run_sobel.sh –cmd -res 1280x720

11 References


12 Appendix


12.1 Vivado HLS Flow for generating Sobel filter Pcore

Vivado HLS provides a tool and methodology for migrating algorithms coded in C, C++ or System-C from the Zynq PS onto the PL by generating RTL code. The Sobel filter IP core used in the Zynq Base TRD was generated using this approach.
Note: Pre-generated Sobel IP cores are available at $ZYNQ_TRD_HOME/hw/pa_proj/zynq_base_trd.srcs/sources_1/edk/xps_proj/pcores/sobel_filter_top_v1_05_a


Synthesizing the HLS Design

1. Launch Vivado HLS .
  • On Windows 7 ,select Start > All Programs > Xilinx Design Tools > Vivado 2013.1 > Vivado HLS.
  • On Linux ,enter vivado_hls at the command prompt.

2. On the Vivado HLS welcome screen, click Open Project under the Getting Started group.
TRD14.5_HLS_WelcomeScreen.png

3. In the Open Project dialog, browse to the $ZYNQ_TRD_HOME/hw/hls_proj/sobel directory and click OK.

TRD14.5_HLS_BrowseForFolder.png


4. From the icon bar, click the Synthesis button to generate the RTL for the algorithm.
TRD14.5_HLS_RunCSynthesis.png

Exporting the RTL as EDK Pcore

1. Click the Export RTL button to package the RTL as EDK Pcore.
TRD14.5_HLS_ExportRTL.png

2. In the dialog box, select Pcore for EDK.

3. Click the Configuration... button.
Enter 1.05.a for the pcore Version and confirm with OK twice.
TRD14.5_HLS_ExportRTL_Pcore_config.png

The Pcore is located in the directory $ZYNQ_TRD_HOME/hw/hls_proj/sobel/solution1/impl/pcores

12.2 EDID Extended display identification data .


The Extended Display Identification Data (EDID) is a data structure, with optional variants, to allow the display to inform the host about its identity and capabilities. The EDID data structure is
independent of the communication protocol used between the monitor and host.

EDID 2.0 Version 2 Revision 0 data structure defined a completely new EDID data structure based on 256-byte records.

To check if a display source supports a particular resolution its EDID information can be queried. There are lot of available software tools for managing EDID information.
Example: Extron EDID Manager® is a software tool that can be a useful aid in troubleshooting potential EDID compatibility issues between a display and the source connected to it. The software allows you to read the display's EDID and generate a report, providing detailed information about the display device.
http://www.extron.com/product/software.aspx?id=edidmanager&s=5

Current Linux framebuffer has in default EDID check enabled , so on switching resolution it will check if connected monitor supports that resolution .
If monitor supports the specified resolution it switches successfully or else return an error.

Note: EDID check can also be disabled by configuring preffered video mode parameter in device tree [ Not recommended ]

Steps for changing the device tree source .

a) Switch to kernel source directory and open device tree source .
vi  $ZYNQ_TRD_HOME/linux-xlnx/arch/arm/boot/dts/zynq-zc702-base-trd.dts
b) Find edid section and set preferred video mode to 0.
edid {
preffered-videomode = <0>;
display-data = <1>;
};
c) Save the current changes and follow the steps mentioned in section 7.2 for building device tree blob.


12.3 Known Issues


a) Occasional image tearing is observed in sobel video output.
b) In QT GUI application , disconnecting and reconnecting monitor hdmi cable , cause GUI Layer to appear on the top. It has no other functional impact.
Explanation- On reconnecting the monitor , frame buffer parameters like fb_var_screeninfo are set to default values as queried during EDID exchange.
In current design QT application is not querying monitor disconnect status , which will be added in coming release.