The purpose of this page is to describe the Linux Phy driver for Xilinx HDMI Video PHY Soft IP for Zynq Ultrascale+ MPSOC


The Xilinx® Video PHY Controller LogiCORE™ IP core is designed for enabling plug-and-play connectivity with Video (DisplayPort and HDMI® technology) MAC Transmit or Receive subsystems. The interface between the video MAC and PHY layers are standardized to enable ease of use in accessing shared transceiver resources. The AXI4-Lite register interface is provided to enable dynamic accesses of transceiver controls/status

Video IP Layer

Driver Overview

The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability. The Video PHY Controller IP/Driver is not intended to be used as a stand alone IP and must be used with Xilinx Video MACs such as HDMI 1.4/2.0 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems.

As such PHY Linux Driver is implemented within the kernel PHY framework and is tightly coupled with HDMI Rx/Tx Linux drivers. This driver also hosts the common video files shared between the 3 Xilinx connectivity drivers (Vphy, HDMI Rx and HDMI Tx) and exports the relevant API’s for inter-driver communication. On kernel boot-up both HDMI Rx & Tx drivers will request 3 PHY lanes each for Rx & Tx and will defer until PNY driver has been initialized.

HW IP Features

  • AXI4-Lite support for register accesses
  • Protocol Support: DisplayPort, HDMI
  • Full transceiver dynamic reconfiguration port (DRP) accesses and transceiver functions
  • Independent TX and RX path line rates (device specific)
  • Single quad support
  • Phase-locked loop (PLL) switching support from software
  • Transmit and Receiver user clocking
  • Protocol specific functions (For example, HDMI Clock Detector)
  • Non-integer data recovery unit (NI-DRU) support for lower line rates. NI-DRU support is for the HDMI protocol only.
  • Advanced Clocking Support (DisplayPort protocol only)

HW IP Configuration

Only below depicted IP configuration is supported at this time

Known Issues and Limitations

  • Only 1 IP configuration supported (listed in HW IP Configuration section)
  • Multiple instances capability not tested
  • Driver does not conform to Linux coding guidelines and is being released as early-access. Consequently driver files will be located in staging area until further notice
  • Supports only HDMI protocol at this time

Kernel Configuration Options for Driver


Device Tree Binding

The dts node should be defined with correct hardware configuration. How to define the node is documented in Documentation/devicetree/bindings/phy/xlnx,vphy.txt

DEBUG Capability

Video PHY Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in kernel dmesg buffer

Boards Supported

Driver has been tested on following boards
  • zcu102 Rev 1.0
  • Zcu106 Rev C

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