The purpose of this page is to describe the Linux DRM driver for Xilinx SDI-Tx Soft IP for Zynq Ultrascale+ MPSOC


The Society of Motion Picture and Television Engineers (SMPTE) UHD-SDI transmitter subsystem implements a SDI transmit interface in accordance to the serial digital interface (SDI) family of standards. The subsystem accepts video from AXI-4 Stream Video interface and outputs. Native Video stream, and allows for fast selection of the top-level parameters and automates most of the lower level parameterization.
The AXI4-stream video interface allows a seamless interface to other AXI4-Stream-based subsystems.
The SMPTE UHD-SDI Transmitter Subsystem allows you to quickly create systems based on SMPTE SDI protocols. It accepts AXI-4 Video stream and outputs native SDI stream by using Xilinx transceivers as physical layer.
The top level customization parameters select the required hardware blocks needed to build the subsystem.

Driver Overview

SDITx is the last node in the display pipeline. The Linux driver is implemented as a sub-component of the Xilinx DRM KMS bridge driver and implements the encoder/connector interface. The subsystem includes the video timing controller(VTC), Axi-4 Stream to Video, SDI Tx bridge and Tx sub-core.
Driver implements the DRM callbacks to read the supported resolutions from driver and provide to DRM framework anytime queried.
On mode change request from user application driver works in conjunction with DRM framework to validate the requested mode to ensure the stream can be generated by Tx core and is supported by the driver. If requested mode is supported the driver will configure Tx sub-core for new mode and the configure the video timing controller (VTC) to generate requisite video timing for it.
This driver also supports user parameters for SDi-mode, number of data stream and fractional frame rates.

HW IP Features

  • Supports SD, HD, 3GA/3GB, 6G or 12G SDI mode
  • Supports 2, 4 or 8 data streams
  • Video lock, GT reset, CE align error, Overflow, Underflow status interrupt
  • Supports ST352 Payload
  • Mode and Transport type detection
    • Fractional / Integral Frame rate
    • Interlaced / Progressive Transport
    • Family detection
  • Supports YUV 422, 10 bits per component, 2 pixels per clock

HW IP Configuration

SDI Mode - 3G, 6G, 12G 8DS

Known Issues & Limitations

  • VTC driver have some issues and thus need to apply a local patch on top of 2017.3 release.
  • Psf and interlaced modes are not entirely correct as VTC driver doesn't support interlaced.
  • Some modes of 3GB and SD could be having issue due to above reason.
  • Supports 2, 4 or 8 data streams
  • Video lock, GT reset, CE align error, Overflow, Underflow status interrupt
  • Tested with only Phabrix SDI generator.
  • ST352 payload aspect ratio and color Colorimetry are not supported yet

Kernel Configuration Options for Driver


Device Tree Binding

The dts node should be defined with correct hardware configuration. How to define the node is documented in

Test Procedure

SDI-Tx can be manually configured to generate the required mode. An open source utility like modetest can be used to configure the display pipeline.
Pipeline: DDR ==> VDMA ==> SDI-Tx

Sample command to set a mode is shown below
  • modetest –M xilinx_drm -s <connector_id>[@<crtc_id>]:<mode>[-<vrefresh>][@<format> - w <connector_id>:<property_name>:<property_value>
For ex:
  • modetest -D amba_pl@0:xilinx_drm_2 -s 27:1280x720-30@YUYV -w 27:sdi_mode:0 -w 27:sdi_data_stream:2 -w 27:is_frac:0
Above command will generate a color bar pattern at requested resolution in DDR, configures the DMA to read the frame from DDR and configures the SDI-TX for said resolution. As a final result Color Bar at defined resolution should be visible on screen.

Debug capability

The driver debug messages can be enabled by adding "#define DEBUG" at the top of the file.
All debug prints are sent to serial console and can be viewed in kernel dmesg buffer.

Boards Supported

Driver has been tested on ZCU106 Rev C

Related Links