The purpose of this page is to describe the Linux DRM driver for Xilinx HDMI Tx Soft IP for Zynq Ultrascale+ MPSOC



Introduction

The HDMI 1.4/2.0 Transmitter Subsystem is a feature-rich soft IP incorporating all the necessary logic to properly interface with PHY layers and provide HDMI® encoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI TX-related IP sub-cores and outputs them as a single IP. The subsystem takes incoming video and audio streams and transfers them to an HDMI stream. The stream is then forwarded to the video PHY layer.

The HDMI 1.4/2.0 Transmitter Subsystem is a MAC subsystem which works with a Video PHY Controller (PHY) to create a video connectivity system. The HDMI 1.4/2.0 Transmitter Subsystem is tightly coupled with the Xilinx Video PHY Controller, which itself is independent and offer flexible architecture with multiple-protocol support. Both MAC and PHY are dynamically programmable through the AXI4-Lite interface.

tx_phy.jpg
MAC Interface with PHY

Driver Overview

HDMI Tx is the last node in the display pipeline. The linux driver is implemented as a sub-component of the Xilinx DRM KMS bridge driver and implements the encoder/connector interface. The subsystem includes the video timing generator and Tx sub-core. Driver implements the DRM callbacks to read the display EDID and present it to the framework anytime a display is connected. It works in tandem with the DRM bridge driver to validates each mode listed in the EDID and reject unsupported modes.

On mode change request from user application driver works in conjunction with DRM framework to validate the requested mode to ensure the stream can be generated by Tx core and is supported by the attached display. If requested mode is supported the driver will configure Tx sub-core for new mode and the internal video timing controller (VTC) to generate requisite video timing for it. It also configures the PHY layer for the new mode and manages all required interaction between MAC & PHY layer.

After mode setup is complete PHY state machine is reset and put into a wait state awaiting the reference clock for the new mode from an external clock source. DRM framework requests the registered clock producer (SI5324/SI5319 for Xilinx HDMI) to generate the clock for desired mode. Availability of this clock is checked by PHY using tx_refclk_rdy port pin. After this pin is asserted HIGH PHY’s internal state machine is triggered to lock onto the incoming frequency and stream transmission starts. As a last step the driver then configures the external LVDS to TMDS level shifter component (DP159), via CCF framework, which will convert the GT output signals to HDMI interface.

IP/Driver Features


IP Feature
2017.1_video_ea
2017.3_video_ea
IP Version Supported
2.0
3.0
HDMI 2.0 and 1.4b compatible
Y
Y
2 or 4 symbol/pixel per clock input (PPC)
2 PPC Only
2 PPC Only
Supports resolutions up to 4,096 x 2,160 @60 fps
Y
Y
8, 10, 12, and 16-bit Deep-color support
8-bit Only
8 & 10-bit Only
Support color space for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0
RGB and YUV 4:2:2 Only
Support all color spaces
Support AXI4-Stream Video output stream and
Native Video output stream
Axi-Stream Video Only
Axi-Stream Video Only
Audio support for up to 8 channels
No Audio Support
No Audio Supported
Optional High Bandwidth Digital Copy Protection (HDCP) 1.4 support
N
Y
Optional HDCP 2.2 support
N
Y
Optional Video over AXIS compliant NTSC/PAL Support
N
N
Optional Video over AXIS compliantYUV420 Support
N
Y

Kernel Configuration Options for Driver

CONFIG_DRM_XILINX_HDMI, CONFIG_VIDEO_XILINX and CONFIG_ PHY_XILINX_VPHY should be enabled

Device Tree Binding

The dts node should be defined with correct hardware configuration. How to define the node is documented in Documentation/devicetree/bindings/drm/xilinx/hdmi-tx-ss.txt

Device Control

Sysfs interface has been added to the driver to enable the user to query the current device status and/or change certain properties. Below table describes the available commands and the access permissions available

Command Name
Permission
Description
hdmi_info
Read-Only by all
Shows detected stream properties
hdmi_log
Read-Only by all
Shows event logs captured by the driver
hdcp_log
Read-Only by all
Shows event logs captured by the driver
hdcp_debugen
Write-Only by group and owner
1: Enable detailed logging of hdcp events
0: Disable detailed logging of hdcp events
(0 is the default)
hdcp_authenticate
Write by group and owner

Read by all
1: enable authentication upon stream up
0: disable
hdcp_encrypt
Write by group and owner

Read by all
1: enable encryption after authentication
0: do not enable encryption after authentication
hdcp_authenticated
Read-Only by all
1: Authentication successful
0: Un-authenticated
hdcp_encrypted
Read-Only by all
1: Input stream is encrypted
0: Input stream is unencrypted
hdcp_protect
Write by group and owner

Read by all
1: content must be protected - If the encrypted flag is not set, then the output will be blanked
0: no protection is required – disable hdcp blank
hdcp_key
R/W by owner only
Allows owner to write the HDCP key binary data (read from EEPROM) to IP
hdcp_password
R/W by owner only
Allows owner to set a password for the hdcp key in eeprom. After writing (first) password
and (then) key, upon reading back hdcp_password it returns "accepted" when the password
could decrypt the key. It reads back "rejected" in all other cases.
vphy_info
Read-Only by all
Shows video_phy status for both Rx and Tx
vphy_log
Read-Only by all
Shows event logs captured by both Rx and Tx

Sysfs entries are accessible at /sys/devices/platform/amba_pl\@0/<device_addr>/

For ex:
To read out information on current set output stream
%> cat /sys/devices/platform/amba_pl\@0/<device_addr>/hdmi_info
To enable detailed logging of hdcp events
%> echo 1 > /sys/devices/platform/amba_pl\@0/<device_addr>/hdcp_debug

HDCP Support

Driver supports HDCP1.4 and 2.2 Protocols and exposes the sysfs controls to allow user space to load the encrypted HDCP production keys and read-in the requisite password to decrypt the keys. If the provided password is able to decrypt the keys, keys will be loaded into the required IP blocks and the HDCP feature will be enabled. The driver boots with HDCP disabled as default state. User can load the keys any time after the system is running. An example application that demonstrates the HDCP key loading process from user space will be provided by Xilinx for customer reference. For details on HDCP Support provided by the soft IP please refer product guide pg235 on Xilinx.com

Disclaimer: It is user’s responsibility to provide and protect the confidential key data. HDCP Keys must be programmed into the EEPROM on the board.

Test procedure

HDMI-Tx can be manually configured to generate the required mode. An open source utility like modetest can be used to configure the display pipeline.
  • DDR ==> FB_Rd (DMA) ==> HDMI_Tx

Sample command to set a mode is shown below
%> modetest –M xilinx_drm -s <connector_id>[@<crtc_id>]:<mode>[-<vrefresh>][@<format>
 

For ex:
%> modetest –M xilinx_drm –s 26@24:1920x1080@YUYV
Above command will generate a color bar pattern at requested resolution in DDR, configures the DMA to read the frame from DDR and configures the HDMI Tx for said resolution. As a final result Color Bar at defined resolution should be visible on screen.

Driver also supports changing output color formats dynamically. Available output color formats supported by DMA engine can be determined using modetest utility as shown below
root@hdmifb_1013_10b_hdcp:~# modetest -M xilinx_drm
Encoders:
id      crtc    type    possible crtcs  possible clones
25      24      TMDS    0x00000001      0xffffffff
 
Connectors:
id      encoder status          name            size (mm)       modes   encoders
26      25      connected       HDMI-A-1        600x340         26      25
  modes:
        name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
  3840x2160 60 3840 4016 4104 4400 2160 2168 2178 2250 flags: phsync, pvsync; type: preferred, driver
  3840x2160 30 3840 4016 4104 4400 2160 2168 2178 2250 flags: phsync, nvsync; type: driver
  3840x2160 30 3840 4016 4104 4400 2160 2168 2178 2250 flags: phsync, pvsync; type: driver
  3840x2160 30 3840 4016 4104 4400 2160 2168 2178 2250 flags: phsync, pvsync; type: driver
  3840x2160 25 3840 4896 4984 5280 2160 2168 2178 2250 flags: phsync, pvsync; type: driver
  3840x2160 24 3840 5116 5204 5500 2160 2168 2178 2250 flags: phsync, pvsync; type: driver
  3840x2160 24 3840 5116 5204 5500 2160 2168 2178 2250 flags: phsync, pvsync; type: driver
  1920x1080 60 1920 2008 2052 2200 1080 1084 1089 1125 flags: phsync, nvsync; type: driver
  1920x1080 60 1920 2008 2052 2200 1080 1084 1089 1125 flags: phsync, pvsync; type: driver
  1920x1080 60 1920 2008 2052 2200 1080 1084 1089 1125 flags: phsync, pvsync; type: driver
  1920x1080 30 1920 2008 2052 2200 1080 1084 1089 1125 flags: phsync, pvsync; type: driver
  1920x1080 30 1920 2008 2052 2200 1080 1084 1089 1125 flags: phsync, pvsync; type: driver
  1920x1080 24 1920 2558 2602 2750 1080 1084 1089 1125 flags: phsync, pvsync; type: driver
  1920x1080 24 1920 2558 2602 2750 1080 1084 1089 1125 flags: phsync, pvsync; type: driver
  1600x900 60 1600 1624 1704 1800 900 901 904 1000 flags: phsync, pvsync; type: driver
  1280x1024 60 1280 1328 1440 1688 1024 1025 1028 1066 flags: phsync, pvsync; type: driver
  1280x800 60 1280 1328 1360 1440 800 803 809 823 flags: phsync, nvsync; type: driver
  1152x864 60 1152 1216 1336 1520 864 865 868 895 flags: nhsync, pvsync; type:
  1280x720 60 1280 1390 1430 1650 720 725 730 750 flags: phsync, pvsync; type: driver
  1280x720 60 1280 1390 1430 1650 720 725 730 750 flags: phsync, pvsync; type: driver
  1024x768 60 1024 1048 1184 1344 768 771 777 806 flags: nhsync, nvsync; type: driver
  800x600 60 800 840 968 1056 600 601 605 628 flags: phsync, pvsync; type: driver
  720x480 60 720 736 798 858 480 489 495 525 flags: nhsync, nvsync; type: driver
  720x480 60 720 736 798 858 480 489 495 525 flags: nhsync, nvsync; type: driver
  640x480 60 640 656 752 800 480 490 492 525 flags: nhsync, nvsync; type: driver
  640x480 60 640 656 752 800 480 490 492 525 flags: nhsync, nvsync; type: driver
  props:
        1 EDID:
                flags: immutable blob
                blobs:
 
                value:
                        00ffffffffffff001e6d085b92a10400
                        031a0103803c2278ea3035a7554ea326
                        0f50542108007140818081c0a9c0d1c0
                        81000101010108e80030f2705a80b058
                        8a0058542100001e04740030f2705a80
                        b0588a0058542100001a000000fd0038
                        3d1e873c000a202020202020000000fc
                        004c4720556c7472612048440a2001d9
                        020330714d902220050403020161605d
                        5e5f230907076d030c002000b83c2000
                        6001020367d85dc401788003e30f0003
                        023a801871382d40582c450058542100
                        001a0000000000000000000000000000
                        00000000000000000000000000000000
                        00000000000000000000000000000000
                        00000000000000000000000000000016
        2 DPMS:
                flags: enum
                enums: On=0 Standby=1 Suspend=2 Off=3
                value: 0
 
CRTCs:
id      fb      pos     size
24      43      (0,0)   (3840x2160)
  3840x2160 60 3840 4016 4104 4400 2160 2168 2178 2250 flags: phsync, pvsync; type: preferred, driver
  props:
 
Planes:
id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
23      24      43      0,0             0,0     0               0x00000001
  formats: XB24 XB30 XR24 XV24 VU24 XV30 YUYV UYVY NV16 NV12 XV15 XV20 BG24 GREY Y10
  props:
        5 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 1
 
Frame buffers:
id      size    pitch
 

Refer Line "formats" that indicates the FrameBuffer DMA IP configuration supports XB24 XB30 XR24 XV24 VU24 XV30 YUYV UYVY NV16 NV12 XV15 XV20 BG24 GREY Y10 color formats. This setting is configured by the DMA driver device tree node property xlnx,vid-formats

DEBUG Capability

HDMI Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in kernel dmesg buffer

Boards Supported

Driver has been tested on following boards
  • zcu102 Rev 1.0
  • zcu106 Rev C

Related Links


Change Log

  • 2017.3
    1. Only HDMI IP version v3 is supported
      1. Note: Default/Released IP version in catalog is v2. v3, which is a HW cost optimized, will be released as a hidden core in the catalog for 2017.3. Linux design/drivers are built upon v3.
      2. Below are the properties that must be modified to pull-in v3 version of the IP's
        • Hdmi_tx_ss: C_HDMI_VERSION 3
        • Vid_Phy: C_INT_HDMI_VER_CMPTBLE 3
    2. Added 10-bit support
    3. Added HDCP Support
    4. Added YUV444 and YUV420 Support