This page contains additional updates and information for XAPP1079.

Simple AMP Bare-metal on Both Cortex-A9 Processors XAPP1079 Updates

XAPP1079 describes a method of starting up both Zynq Cortex-A9 processors, with CPU0 running bare-metal, and CPU1 running bare-metal. The included design contains a core that generates interrupts towards CPU1. As CPU1 services the interrupt, it communicates with the bare-metal application running on CPU0.

The application note is available at xapp1079

The following list summarizes the additional sections covered on this page:
  • Updated Design Files for EDK14.5
  • Updated Design Files for EDK14.6
  • Updated Design Files for Vivado 2014.1
  • Updated Design Files for Vivado 2014.2
  • Updated Design Files for Vivado 2015.2

Updated Design Files for EDK14.5


The design files have been updated for EDK14.5.

The differences between the EDK14.3 and EDK14.5 designs are:
  • The linker file for both CPU0 and CPU1's application has been updated to work with EDK14.5 BSP
  • The standalone BSP, in the repository, has been updated to match standalone_v3_09_a with a few customizations to work with the XAPP
  • FSBL now supports multiple ELF files so the customized FSBL has been removed from the repository and the dummy cpu1_bootvec.bin file is no longer required so it has been removed from the bootgen.bif file.
  • The XPS project has been rev'd to EDK14.5

Since the FSBL in EDK14.5 supports multiple ELF files, continue following the steps documented in the XAPP but during creation of the FSBL, select the template 'Zynq FSBL'. The 'Zynq FSBL for AMP' template is no longer required and has been removed from the design.

The new design files for EDK14.5 are available here:


Updated Design Files for EDK14.6


The design files have been updated for EDK14.6. The only difference between EDK14.5 and EDK14.6 is the modified standalone BSP is updated from v3_09_a to v3_10_a.


Updated Design Files for Vivado 2014.1


The design files have been updated for Vivado 2014.1. There have often been questions regarding how to reset and control cpu1 so the design has been changed to reset cpu1 and send it to the application instead of relying on the wfe loop that the bootrom sends cpu1 to. Creation of the design now uses tcl within Vivado. There are scripts and instructions to target the following boards: ZC702, ZC706, and ZedBoard. The design includes the source, and generated files that have been tested on ZC702, ZC706 and ZedBoard development boards. This design is early access for the next xapp update.

New: 29jul14: added missing ZedBoard scripts and included all generated files.

Updated Design Files for Vivado 2014.2


The design files have been updated for Vivado 2014.2. There have often been questions regarding how to reset and control cpu1 so the design has been changed to reset cpu1 and send it to the application instead of relying on the wfe loop that the bootrom sends cpu1 to. Creation of the design now uses tcl within Vivado. There are scripts and instructions to target the following boards: ZC702, ZC706, and ZedBoard. The design includes the source, and generated files that have been tested on ZC702 and ZC706. The generated files for the ZedBoard are also included but have not been tested. This design is early access for the next xapp update.

Updated Design Files for Vivado 2015.2


The design files have been updated for Vivado 2015.2. There have often been questions regarding how to reset and control cpu1 so the design has been changed to reset cpu1 and send it to the application instead of relying on the wfe loop that the bootrom sends cpu1 to. Creation of the design now uses tcl within Vivado. There are scripts and instructions to target the following boards: ZC702, ZC706, and ZedBoard. The design includes the source, and generated files that have been tested on ZC702 and ZC706. The generated files for the ZedBoard are not included. This design is early access for the next xapp update.