This page shows how to create a design to simulate a Master full AXI4 interface to validate it. The IP validated is the IP created in this wiki page.
To validate the AXI4 interface, we will use the AXI Verification IP which can simulate AXI4, AXI4-Lite and AXI3 interfaces. It also gives errors if there are issues with the interface (i.e. the interface does not comply with the AXI specification)

Step 1 : Create a new Vivado 2017.1 project

Open Vivado 2017.1 and create a new project targeting the Xilinx ZC702 board

Step 2 : Add the custom IP to the IP repository

In vivado 2017.1, click on Tools > Settings > IP > Repository and add the path to the IP.


Step 3 : Create the Block Design

Create a block Design and add the custom IP (myAXI4IP). Configure the custom IP (myAXI4IP) by setting the Slave Base Address to 0x00000000. Then add an AXI Verification IP (AXI VIP). And configure it as a Slave. It will act like a memory.

VIP_1.png



We can note the following lines in the bottom of the VIP GUI:

VIP_GUI.png

Connect the Master AXI4 interface of the IP to test to the slave interface of the VIP.
Right click on the ports aclk and aresetn of the VIP and click Make External. Connect the ports m00_axi_aclk and m00_axi_aresetn of the custom IP to these external ports.
Right click on the port m00_axi_init_axi_txn of the custom IP and click Make External.

VIP_3.png



In the address editor tab, map the VIP to the address 0x00000000

VIP_4.png



Validate the design, create the HDL wrapper and generate the BD output products.

Step 4 : Create the Test Bench

Create a new simulation source file of type systemVerilog (the VIP only works with systemVerilog).
Edit the file as following:

1. Add the required packages as mentioned in the VIP GUI:
import axi_vip_v1_0_1_pkg::*;
import design_1_axi_vip_slv_0_pkg::*;
 
2. Declare the test bench signals:
bit aclk = 0;
bit aresetn=0;
bit pulse_inp=0;
always #5ns aclk = ~aclk;
 
3. Instantiate the BD:
design_1_wrapper DUT
(
    . aclk (aclk),
    .aresetn(aresetn),
    . m00_axi_init_axi_txn (pulse_inp)
);
 
4. Declare the agent for the VIP (one agent for one AXI VIP has to be declared). We want the VIP to act as a Slave with a memory model. Thus the type of the agent will be <component_name>_slv_mem_t.
// Declare agent
design_1_axi_vip_0_0_slv_mem_t      slv_mem_agent;
5.Create a procedural block with the following:
  • Create a new agent and pass the hierarchy path of IF correctly into the new function
  • Set a tag for agents for easy debug
  • set print out verbosity level for the agent
  • Start the agent
initial begin
    //Create an agent
    slv_mem_agent = new("slave vip agent",DUT.design_1_i.axi_vip_0.inst.IF);
 
    // set tag for agents for easy debug
    slv_mem_agent.set_agent_tag("Slave VIP");
 
    // set print out verbosity level.
    slv_mem_agent.set_verbosity(400);
 
    //Start the agent
    slv_mem_agent.start_slave();
end
 
6. Then create the stimuli for the IP:
initial begin
 
    #50ns
    aresetn = 1;
 
    #50ns
    pulse_inp = 1;
 
    #10ns
    pulse_inp = 0;
 
    #70us
    aresetn = 1;
 
end

The full test bench file is given here:


Step 5 : Launch the simulation


Run the simulation for 70us.

In the TCL console, the VIP gives information on the AXI transactions done:
VIP_5.png


The simulation does not stop on an error (in the TCL console), thus the interface seems to follow the AXI specification.
We can also add the AXI signals in the waveform window to see the AXI transactions:

VIP_6.png

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