SD Controller


Introduction


The SD/SDIO controller communicates with SDIO devices, SD memory cards, and MMC cards with up to four data lines. On the SD interface, one (DAT0) or four (DAT0-DAT3) lines can be used for data transfer. The SDIO interface can be routed through the MIO multiplexer to the MIO pins or through the EMIO to SelectIO pin in the PL.

U-Boot Configuration


For ZynqMP

CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_CMD_MMC=y

For Zynq


CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPL_DM_MMC=y
CONFIG_DFU_MMC=y
CONFIG_CMD_MMC=y

Device Tree


&sdhci1 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sdhci1_default>;
        no-1-8-v;
        xlnx,mio_bank = <1>;
};
 
        pinctrl_sdhci1_default: sdhci1-default {
                mux {
                        groups = "sdio1_0_grp";
                        function = "sdio1";
                };
 
                conf {
                        groups = "sdio1_0_grp";
                        slew-rate = <SLEW_RATE_SLOW>;
                        io-standard = <IO_STANDARD_LVCMOS18>;
                        bias-disable;
                };
 
                mux-cd {
                        groups = "sdio1_0_cd_grp";
                        function = "sdio1_cd";
                };
 
                conf-cd {
                        groups = "sdio1_0_cd_grp";
                        bias-high-impedance;
                        bias-pull-up;
                        slew-rate = <SLEW_RATE_SLOW>;
                        io-standard = <IO_STANDARD_LVCMOS18>;
                };
 
                mux-wp {
                        groups = "sdio1_0_wp_grp";
                        function = "sdio1_wp";
                };
     conf-wp {
                        groups = "sdio1_0_wp_grp"
            bias-high-impedance;
                        bias-pull-up;
                        slew-rate = <SLEW_RATE_SLOW>;
                        io-standard = <IO_STANDARD_LVCMOS18>;
                };
        };
 

Test Procedure


ZynqMP> mmc list
sdhci@ff160000: 0 (eMMC)
sdhci@ff170000: 1 (SD)
ZynqMP> mmc dev 0
switch to partitions #0, OK
mmc0(part 0) is current device
ZynqMP> mmc info
Device: sdhci@ff160000
Manufacturer ID: 11
OEM: 100
Name: 008G7
Tran Speed: 200000000
Rd Block Len: 512
MMC version 5.0
High Capacity: Yes
Capacity: 7.3 GiB
Bus Width: 4-bit
Erase Group Size: 512 KiB
HC WP Group Size: 4 MiB
User Capacity: 7.3 GiB WRREL
Boot Capacity: 4 MiB ENH
RPMB Capacity: 4 MiB ENH
ZynqMP> mmc dev 1
switch to partitions #0, OK
mmc1 is current device
ZynqMP> mmc info
Device: sdhci@ff170000
Manufacturer ID: 3
OEM: 5344
Name: SU04G
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 3.7 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
ZynqMP>
 

Features



Zynq:

The two SDIO controllers are controlled and operate independently with the same feature set:

Host mode controller
  • Four I/O signals (MIO or EMIO)
  • Command, Clock, CD, WP, Pwr Ctrl (MIO or EMIO)
  • Interrupt driven
  • AHB master-slave interface operating at the CPU_1x clock rate
  • Master mode for DMA transfers (with 1 KB FIFO)
  • Slave mode for register accesses

SDIO Specification 2.0
  • Low-speed, 1 KHz to 400 KHz
  • Full-speed, 1 MHz to 50 MHz (25 MB/sec)
  • High-speed and high-capacity memory cards

ZynqMP


Compliance
  • SD Host Controller Standard Specification Version 3.00
  • SDIO card specification Version 3.0
  • SD Memory Card Specification Version 3.01
  • SD Memory Card Security Specification version 1.01
  • MMC Specification version 4.51
  • OCP specification version 2.01(For the Host Controller with OCP Interface)
  • AMBA AHB Specification version 2.00 (For the Host Controller with AHB Interface)
  • AMBA AXI Specification version 3.00 (For Host Controller with AXI Interface)

System/Host Interface
  • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
  • Data transfer using PIO mode on the Host Bus Slave interface, using DMA mode on the Host Bus Master interface. Here the Host Bus is AHB or AXI or OCP Interface.

SD/SDIO Card interface
  • Host clock rate variable between 0 and 208 MHz
  • Up to 832Mbits per second data rate using 4 parallel data lines (SDR104 mode)
  • Transfers the data in 1 bit and 4 bit SD modes
  • Transfers the data in SDR104, SDR50, DDR50 modes.
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Variable-length data transfers
  • Performs Read wait Control, Suspend/Resume operation SDIO CARD.
  • Designed to work with I/O cards, Read-only cards and Read/Write cards
  • Supports Read wait Control, Suspend/Resume operation

MMC card interface
  • Host clock rate variable between 0 and 208 MHz
  • Up to 1664Mbits per second data rate using 8 bit parallel data lines (mmc8 bit SDR mode)
  • Up to 832Mbits per second data rate using 8 bit parallel data lines (mmc8 bit DDR mode)
  • Transfers the data in 1 bit, 4 bit and 8 bit modes
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Supports MMC Plus and MMC Mobile
  • Card Detection (Insertion / Removal)



SD Controller:
Introduction
The SD/SDIO controller communicates with SDIO devices, SD memory cards, and MMC cards with up
to four data lines. On the SD interface, one (DAT0) or four (DAT0-DAT3) lines can be used for data
transfer. The SDIO interface can be routed through the MIO multiplexer to the MIO pins or through
the EMIO to SelectIO pin in the PL.