Introduction


This page gives an overview of standalone BSP which is available as part of the Xilinx Vivado and SDK distribution.

Source path for the driver:

https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone

Standalone BSP source code is organized into different folders. Below diagram shows the BSP source organization

Standalone
|
-- doc - Provides the information about APIs and
|
-- src - Source files for BSP

Overview:

Xilinx provides support for Microblaze, Cortex-A9, Cortex-R5 and Cortex-A53 processors.
The standalone BSP performs the processor bring up and provides interface to the user to carry out processor related functionalities naming a few Interrupt enable/disable, device configuration, cache access etc.

To build the BSP, default toolchains are configured with the help of CPU driver. The CPU drivers configure toolchain, archiver and extra compiler flag related settings for a particular bsp. The BSP and drivers are compiled with the same settings. The code for cpu driver can be found at:
cpu_cortexa53 (for Cortex-A53)
cpu_cortexa9 (for Cortex-A9)
cpu_cortexr5 (for Cortex-R5)
cpu (for Microblaze)

The application is built on top of standalone BSP and drivers. The application starts with boot code, doing the processor initialization, soc configuration if required any, toolchain related functionalities if required and reaching to application main. The BSP provide simplified interface to access processor and soc related functionalities.

Features Supported:

ARM Processors (Cortex-A9, Cortex-R5, Cortex-A53):

Common Features in ARM BSP:

  • Boot code
  • Cache Flush/Invalidation
  • Interrupt/Exception handling
  • Lite printf version (xil_printf)
  • Memory/IO access through APIs
  • Sleep functionality with busy loop
  • C interface for frequently used assembly instructions
  • Endianness: Little endian

Cortex-A9 BSP supported features:

  • Device/Memory attribute configuration in MMU as per requirement (Default configuration is done by Boot code)
  • Floating point support
  • Nested interrupt support
  • Snoop control unit
  • Global timer access
  • Execution at System Mode
  • Different compiler support:
    • gcc
    • armcc
    • iar

Cortex-R5 BSP supported features:

  • Device/Memory attribute configuration in MPU as per requirement (Default configuration is done by Boot code)
  • Vectors in TCM for low latency interrupt
  • Nested interrupt support
  • Execution at System Mode
  • gcc and IAR compiler support

Cortex-A53 BSP supported features:

  • AArch64 and AArch32 mode
  • Execution at Secure Monitor Level EL3 for AArch64 and System mode for AArch32
  • AAech64 BSP supports EL1 Non-secure execution on hypervisor
  • Device/Memory attribute configuration in MMU as per requirement (Default configuration is done by Boot code)
  • Generic counter accessibility
  • gcc compiler support
  • Floating point support

Boot Sequence for ARM Processors:

When application software needs to be executed on processor, there are certain configuration needs to be done which are done as part of boot code. When an application is built with Xilinx standalone bsp, following is a sequence illustrating how an application starts and reaches to main function.
  • Program vector table base for exception handling
  • Invalidate cache, TLBs
  • Program stack pointer for various modes
  • Configure MMU/MPU
  • Enable data cache, instruction cache and MMU/MPU
  • Clearing of BSS sections
  • Running global constructor
  • Jumping to application main

MMU/MPU Configuration for ARM Processors

  • MMU configuration:
    • The translation table is a flat mapped (input address is same as output address) static translation table. The size of the pages in translation table is decided based on the processor architecture and platform requirement. The attribute of the particular page in a translation table are defined as per the default address map, and they can be changed as per user need during main application by using an API provided by BSP.
  • MPU Configuration:
    • There are limited number of regions which can be configured to denote the attributes in MPU. Some of the regions are configured by default at the time of booting of the processor as per architecture and platform requirement. The remaining regions can be utilized by user in the application main to configure as per their requirement using BSP API.

Known issues and Limitations

  • Cortex-a53 AArch64 EL1 NS executio : qspipsu, nandpsu, ipipsu drivers and lwip library does not work with the EL1 NS execution over hypervisor.

Changelog


2017.4:

  • Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc.

2017.3:

  • Added hard floating point support in Cortex a53 32 bit BSP
  • Added EL1 NS mode support for platform version related APIs
  • Revamps the way MPU regions are handled.New APIs are added to make MPU access user friendly. A bug where the existing logic was allowing users to go beyond 16 regions is fixed
  • Implemented ARM erratum 855873
  • Marked memory as a outer shareable for EL1 NS execution in Cortex a53 64 bit translation table
  • Fixed bug in Xil_In32BE
  • Added support for PMUFW in XGetPlatform_Info API
  • Fixed bug in EL1 NS mode IRQInterruptHandler

2017.2

  • Added hard floating point support in the cortex-R5 BSP
  • Updated Cortex-a53 32 bit BSP boot code to fix bug in the HW coherency enablement.
  • Updated Cortex-a53 64 bit BSP boot code, to remove redundant write to the L2CTLR_EL1 register.

2017.1

  • Added support for Cortex-A53 64bit EL1 Non-secure execution on hypervisor. If hypervisor_guest is set true in bsp settings, it will be compiled for EL1 Non-secure, else it will be compiled for EL3. By default Cortex A53 64bit BSP is built for EL3 Secure Monitor.
  • Modified Cortex-A53 translation table for upper ps DDR. The 0x800000000 - 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf and rest of the memory in that 32GB region is marked as reserved to avoid any speculative access
  • Added IAR compiler support for Cortex R5 BSP
  • Added support for Floating point access for Cortex-A53 64bit mode standalone BSP. Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it contains initial status of FPU i.e. disabled. In case of a warm restart execution when bss sections are not cleared, it may contain previously updated value which does not hold true once processor resumes.
  • Added arm/cortexa53/64bit/xil_smc.c, xil_smc.h files to provide a C wrapper for smc calling which can be used by cortex-A53 64bit EL1 Non-secure application
  • The MB intrusive profiling when enabled was causing a crash because of invalid HSI command being used. Corrected standlone.tcl script to fix this issue.
  • Updated standalone.tcl script to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if any FPD peripheral is configured to use CCI.It wll be used by pmufw to know, whether any FPD peripheral is configured for CCI. This change is applicable only for psu_pmu processor bsp.
  • Added API Xil_MemCpy for word alinged data access
  • Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean target over windows.
  • Add safe Xil_Out32 implementation
  • The existing Xil_DCacheDisable API first flushes the D caches and then disables it. The problem with that is, potentially there will be a small window after the cache flush operation and before the we disable D caches where we might have valid data in cache lines. In such a scenario disabling the D cache can lead to unknown behavior. The ideal solution to this is to use assembly code for the complete API and avoid any memory accesses. But with that we will end up having a huge amount on assembly code which is not maintainable. Changes are done to use a mix of assembly and C code. All local variables are put in registers. Also function calls are avoided in the API to avoid using stack memory.
  • The new api Xil_ConfigureL1Prefetch is added to disable pre-fetching/configure maximum number of outstanding data prefetches allowed in L1 cache system
  • Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.

2016.4

  • Defined interrupt IDs for FPD_SWDT and LPD_SWDT in xparameters_ps.h for Cortex-R5 and Cortex-A53.
  • Modified CortexA9 translation table to correct explanation for memory attributes
  • Corrected interrupt ID number for FPGA in xparameters_ps.h of Cortex-R5 and Cortex-A53.

2016.3

  • Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot section since it is part of boot process. This is to fix a hang caused when application is ran from OCM and vector table & boot code in TCM with vectors as HIVEC.
  • Program the counter frequency in boot code for CortexA53
  • Updated the sleep_common function in microblaze_sleep.c.
  • Restructured the BSP to avoid code duplication across all BSPs. Source code directories specific to ARM processor's are moved to src/arm directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h, xil_exception.c and xil_exception.h are consolidated across all ARM BSPs into common file each and consolidated files are kept at src/arm/common directory.GCC files related to file operations are consolidated and kept at src/arm/common/gcc directory. All io interfacing functions (i.e. All variants of xil_out, xil_in ) are made as static inline and implementation is kept in consolidated common/xil_io.h,xil_io.h must be included as a header file to access io interfacing functions.
  • Added undefined exception handler for A53 32 bit and R5 processor. Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since TTC counter value register is read only.
  • Removed unused variables from xil_printf.c and xplatform_info.c
  • Defined ARMA53_32 and ARMR5 flag in cortexa53/32bit/xparameters_ps.h and cortexr5/xparameters_ps.h respectively.
  • Added support for zynq 7000s (single core) devices
  • Modified xil_io.h to remove LITTLE_ENDIAN flag check for all ARM processors.

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