Introduction

This page gives an overview of sdps driver which is available as part of the Xilinx Vivado and SDK distribution.

Source path for the driver:

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/sdps/


Driver source code is organized into different folders. Below diagram shows the sdps driver source organization

sdps
|
-- Doc - Provides the API and data structure details
|
- Source - Driver source files

Features Supported by controller

Compliance
• SD Host Controller Standard Specification Version 3.00
• SDIO card specification Version 3.0
• SD Memory Card Specification Version 3.01
• SD Memory Card Security Specification version 1.01
•MMC Specification version 4.51
• OCP specification version 2.01(For the Host Controller with OCP Interface)
• AMBA AHB Specification version 2.00 (For the Host Controller with AHB Interface)
• AMBA AXI Specification version 3.00 (For Host Controller with AXI Interface)

System/Host Interface
• Supports one of the following System/Host Interfaces: AHB, AXI or OCP
• Data transfer using PIO mode on the Host Bus Slave interface, using DMA mode on the Host Bus Master interface. Here the Host Bus is AHB or AXI or OCP Interface.

SD/ SDIO Card interface
• Host clock rate variable between 0 and 208 MHz
• Up to 832Mbits per second data rate using 4 parallel data lines (SDR104 mode)
• Transfers the data in 1 bit and 4 bit SD modes
• Transfers the data in SDR104, SDR50, DDR50 modes.
• Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
• Variable-length data transfers
• Performs Read wait Control, Suspend/Resume operation SDIO CARD.
• Designed to work with I/O cards, Read-only cards and Read/Write cards
• Supports Read wait Control, Suspend/Resume operation

MMC card interface
• Host clock rate variable between 0 and 208 MHz
• Up to 1664Mbits per second data rate using 8 bit parallel data lines (mmc8 bit SDR mode)
• Up to 832Mbits per second data rate using 8 bit parallel data lines (mmc8 bit DDR mode)
• Transfers the data in 1 bit, 4 bit and 8 bit modes

Driver supported features

  • 1, 4, 8 bit bus width
  • Speed Modes – Default [Normal], High speed, SDR12, SDR25, SDR50, SDR104, DDR50, HS200
  • ADMA2 transfers
  • Polled mode
  • Switch command

Known issues and Limitations

Driver supports only polled mode.

Performance

SD card : Sandisk Ultra 16GB SDHC card

Zynq:
High speed
20.54 MB/sec
ZynqMP:
High Speed
19.4 MB/Sec
SDR
SDR104: 76.50MB/sec
DDR
DDR50: 40.68MB/sec
Note : The SD performance may be impacted by the SD card cluster size. Formatting the card with larger cluster size will be able to produce higher performance. Above performance numbers are achieved by formatting the SD card with highest possible cluster size.

Test cases

The file system example is xilffs_polled_example.c
This file system example creates a new file in an SD/eMMC card (formatted with file system) writes a sequence into the files and reads it back to verify. This example can be modified to write user data to a file or read existing files as required. The API’s are standard file system API’s.

Changelog

2016.3

  • Added support for mkfs in the sd driver. It will calculate the sector size and number of sectors to identify the card capacity.
  • Used usleep API across all the platforms, since MB_SLEEP API is deprecated.
  • Added bus_width, mio_bank and has_emio parameters to tcl file to export to xparameters.h
  • Added support for UHS mode switching based on the card capability.
  • Added Tap delays inside the drivers required for High Speed modes and UHS modes.

2016.4

  • Reduce the delay during power cycle from one second to one milli second.
  • Used emmc_hwreset pin to reset eMMC card rather than relying on power cycle.
  • Enable Rst_n bit in EXT_CSD reg if disabled - This is to enable hw reset functionality in eMMC device.
  • Implemented revived auto-tuning workaround by implementing dll_reset during tuning process.

2017.1

  • Corrected voltage switching sequence as per TRM.
  • Fixed Compilation warnings - CR#957004
  • Add DDR and HSD support for eMMC
  • Support for bus width switching based on hdf
  • Added support for A53-32bit on ZynqMP.
  • Fixed MISRAC mandatory violation - CR#970531
  • Fixed UR data flow anomalies
  • Add support in EL1 non secure mode

2017.2

  • None

2017.3

  • Added support for 200MHz in SD
  • Added support for 64bit DMA addressing
  • Added support for CCI in SD
  • Modified Tap Delay settings to avoid potential data corruption