Introduction

Zynq

The SD/SDIO controller is compatible with the standard SD Host Controller Specification Version 2.0 Part A2 with SDMA (single operation DMA), ADMA1 (4 KB boundary limited DMA), and ADMA2 (ADMA2 allows data of any location and any size to be transferred in a 32-bit system memory - scatter-gather DMA) support. The core also supports up to seven functions in SD1, SD4, but does not support SPI mode. It does support SD high-speed (SDHS) and SD High Capacity (SDHC) card standards.

Zynqmp

The “Arasan SD3.0 / SDIO3.0 / eMMC4.51 Host Controller”(3MCR Host Controller) is a Host Controller with a AHB/AXI/OCP processor interface. This product conforms to SD Host Controller Standard Specification Version 3.00.
The 3MCR Host Controller handles SDIO/SD Protocol at transmission level, packing data, adding cyclic redundancy check (CRC), Start/End bit, and checking for transaction format correctness.
The 3MCR Host Controller provides Programmed IO method and DMA data transfer method. In programmed IO method, the Host processor transfers data using the Buffer Data Port Register. Host controller support for DMA can be determined by checking the DMA support in the Capabilities register. DMA allows a peripheral to read or write memory without the intervention from the CPU. The 3MCR Host Controller’s Host Controller system address register points to the first data address, and data is then accessed sequentially from that address.

HW/IP features

Zynq

The two SDIO controllers are controlled and operate independently with the same feature set:
Host mode controller
  • Four I/O signals (MIO or EMIO)
  • Command, Clock, CD, WP, Pwr Ctrl (MIO or EMIO)
  • LED control, bus voltage (EMIO)
  • Interrupt or polling driven
  • AHB master-slave interface operating at the CPU_1x clock rate
  • Master mode for DMA transfers (with 1 KB FIFO)
  • Slave mode for register accesses
SDIO Specification 2.0
  • Low-speed, 1 KHz to 400 KHz
  • Full-speed, 1 MHz to 50 MHz (25 MB/sec)
  • High-speed and high-capacity memory cards

ZynqMP

Compliance
  • SD Host Controller Standard Specification Version 3.00
  • SDIO card specification Version 3.0
  • SD Memory Card Specification Version 3.01
  • SD Memory Card Security Specification version 1.01
  • MMC Specification version 4.51
  • OCP specification version 2.01(For the Host Controller with OCP Interface)
  • AMBA AHB Specification version 2.00 (For the Host Controller with AHB Interface)
  • AMBA AXI Specification version 3.00 (For Host Controller with AXI Interface)
System/Host Interface
  • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
  • Data transfer using PIO mode on the Host Bus Slave interface, using DMA mode on the Host Bus Master interface. Here the Host Bus is AHB or AXI or OCP Interface.
SD/SDIO Card interface
  • Host clock rate variable between 0 and 208 MHz
  • Up to 832Mbits per second data rate using 4 parallel data lines (SDR104 mode)
  • Transfers the data in 1 bit and 4 bit SD modes
  • Transfers the data in SDR104, SDR50, DDR50 modes.
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Variable-length data transfers
  • Performs Read wait Control, Suspend/Resume operation SDIO CARD.
  • Designed to work with I/O cards, Read-only cards and Read/Write cards
  • Supports Read wait Control, Suspend/Resume operation
MMC card interface
  • Host clock rate variable between 0 and 208 MHz
  • Up to 1664Mbits per second data rate using 8 bit parallel data lines (mmc8 bit SDR mode)
  • Up to 832Mbits per second data rate using 8 bit parallel data lines (mmc8 bit DDR mode)
  • Transfers the data in 1 bit, 4 bit and 8 bit modes
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Supports MMC Plus and MMC Mobile
  • Card Detection (Insertion / Removal)

What's new in Zynqmp
  1. SD
    • UHS speed modes
    • 1.8V capability
    • SDXC card capacity support (>64G)
    • Tuning procedure for SDR104/DDR50/SDR50
    • voltage switch, tuning commands
  2. eMMC
    • complete new spec handled by JEDEC compared to MMC association
    • HS200 mode and Extended CSD register to support various features
    • 1.8V/1.2V support from CMD0
    • DDR mode support
    • 8-bit bus width
    • Tuning, bus width testing procedures
    • variants of erase - secure/trim/discard/sanitize
    • boot partitions, boot mode alternate boot mode
    • RPMB partitions

Features supported by driver

Zynq

  • All the HW/IP features are supported by driver

ZynqMP


  • All the HW/IP features are supported by driver


Missing features, known Issues, limitations

  • SD UHS modes support is disabled in the driver currently due to board and silicon dependencies. Not all boards are having 3.0 level shifter

Kernel configurations

config MMC_SDHCI_OF_ARASAN
 
        tristate "SDHCI OF support for the Arasan SDHCI controllers"
        depends on MMC_SDHCI_PLTFM
        depends on OF
        help
 
          This selects the Arasan Secure Digital Host Controller Interface
          (SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC.
          If you have a controller with this interface, say Y or M here.
          If unsure, say N.
 
 
<M> Sound card support  --->
 
HID support  --->
[*] USB support  --->
<M> Ultra Wideband devices  --->
<*> MMC/SD/SDIO card support  --->
<M> Sony MemoryStick card support  --->
-*- LED Support  --->
 
 
 --- MMC/SD/SDIO card support
 
[ ]   MMC debugging
[ ]   MMC host clock gating (NEW)
*** MMC/SD/SDIO Card Drivers ***
 <M>   MMC block device driver
(8)     Number of minors per block device (NEW)
[*]     Use bounce buffer for simple hosts
< >   SDIO UART/GPS class support
< >   MMC host test driver
*** MMC/SD/SDIO Host Controller Drivers ***
<*>   Secure Digital Host Controller Interface support
< >     SDHCI support on PCI bus
[*]       Ricoh MMC Controller Disabler
<*>     SDHCI platform and OF driver helper
<*>       SDHCI OF support for the Arasan SDHCI controllers (NEW)
< >   SDHCI support for Fujitsu Semiconductor F_SDH30 (NEW)
< >   TI Flash Media MMC/SD Interface support
< >   MMC/SD driver for Ricoh Bay1Controllers
< >   ENE CB710 MMC/SD Interface support
< >   VIA SD/MMC Card Reader Driver
 
 
 

Devicetree

SD and eMMC
sdhci@ff160000 {
    compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
    interrupt-parent = <&gic>;
    interrupts = <0x0 0x30 0x4>;
    reg = <0x0 0xff160000 0x0 0x1000>;
    clock-names = "clk_xin", "clk_ahb";
    xlnx,device_id = <0x0>;
};
sdhci@ff170000 {
    compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
    interrupt-parent = <&gic>;
    interrupts = <0x0 0x31 0x4>;
    reg = <0x0 0xff170000 0x0 0x1000>;
    clock-names = "clk_xin", "clk_ahb";
    xlnx,device_id = <0x0>;
};

Performance

SD card : Sandisk Ultra 16GB SDHC card

Zynq:
High speed
20.54 MB/sec
read speed, tool: hdparm
ZynqMP:
High Speed
19.4 MB/Sec
read speed, tool: hdparm
UHS (SDR)
SDR104: 76.50MB/sec
read speed, tool: hdparm
UHS (DDR)
DDR50: 40.68MB/sec
read speed, tool: hdparm
Note : ZynqMP platform will support 'High Speed' mode by default. To operate the SD on UHS (Ultra High Speed) modes, please click here.

Test Procedure

Read/Write test using File System
mkfs.vfat -F 32 /dev/mmcblk0(p1)
mount /dev/mmcblk0(p1) /mnt
mkdir /mnt/sd
vi /mnt/sd/sd.txt
umount /mnt
Read/Write test using DD commands
dd if=/dev/urandom of=/tmp/data bs=1M count=10
dd if=/tmp/data of=/dev/mmcblk0(p1) bs=1M count=10
dd if=/dev/mmcblk0(p1) of=/tmp/data1 bs=1M count=10
 
md5sum /tmp/data /tmp/data1
(sha values reported by md5sum should be equal for data and data1 files
Create partition using FDISK
List Partitions:
 
-----------------------------------
 
fdisk -l /dev/mmcblk0
 
[ 1307.186442] mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
 
Disk /dev/mmcblk0: 3947 MB, 3947888640 bytes
 
4 heads, 16 sectors/track, 120480 cylinders
 
Units = cylinders of 64 * 512 = 32768 bytes
 
        Device Boot      Start         End      Blocks  Id System
 
/dev/mmcblk0p1               1           1          24   b Win95 FAT32
 
/dev/mmcblk0p2               2           2          32  83 Linux
 
Create Partition:
 
-----------------------------------
 
fdisk /dev/mmcblk0
 
[ 1344.587085] mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
 
The number of cylinders for this disk is set to 120480.
 
There is nothing wrong with that, but this is larger than 1024,
 
and could in certain setups cause problems with:
 
1) software that runs at boot time (e.g., old versions of LILO)
 
2) booting and partitioning software from other OSs
 
   (e.g., DOS FDISK, OS/2 FDISK)
 
Command (m for help): n
 
Command action
 
   e   extended
 
   p   primary partition (1-4)
 
p
 
Partition number (1-4): 3
 
First cylinder (3-120480, default 3): 3
 
Last cylinder or +size or +sizeM or +sizeK (3-120480, default 120480): 3
 
Command (m for help): w
 
The partition table has been altered.
 
Calling ioctl() to re-read partition table
 
[ 1832.815341] mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
 
[ 1832.833339]  mmcblk0: p3
 
Different options:
 
--------------------------------------
 
Command (m for help): m
 
Command Action
 
a       toggle a bootable flag
 
b       edit bsd disklabel
 
c       toggle the dos compatibility flag
 
d       delete a partition
 
l       list known partition types
 
n       add a new partition
 
o       create a new empty DOS partition table
 
p       print the partition table
 
q       quit without saving changes
 
s       create a new empty Sun disklabel
 
t       change a partition's system id
 
u       change display/entry units
 
v       verify the partition table
 
w       write table to disk and exit
 
 
Read/Write using File System:
 
---------------------------------------
 
root@Xilinx-ZynqMP-2015_3:~# mkfs.vfat -F 32 /dev/mmcblk0p3
 
[  598.662380] mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
 
[  598.686123] mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
 
root@Xilinx-ZynqMP-2015_3:~# mount /dev/mmcblk0p3 /mnt
 
[  632.450944] mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
 
[  632.519516] mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
 
[  632.558846] mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
 
root@Xilinx-ZynqMP-2015_3:~# mkdir /mnt/sd
root@Xilinx-ZynqMP-2015_3:~# vi /mnt/sd/sd.txt
root@Xilinx-ZynqMP-2015_3:~# umount /mnt

Expected output

Boot log for SD
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
sdhci-arasan ff160000.sdhci: No vmmc regulator found
sdhci-arasan ff160000.sdhci: No vqmmc regulator found
mmc0: SDHCI controller on ff160000.sdhci [ff160000.sdhci] using ADMA 64-bit
sdhci-arasan ff170000.sdhci: No vmmc regulator found
sdhci-arasan ff170000.sdhci: No vqmmc regulator found
mmc1: SDHCI controller on ff170000.sdhci [ff170000.sdhci] using ADMA 64-bit
 
........
 
mmc0: new high speed SDHC card at address 1234
mmcblk0: mmc0:1234 SA04G 3.63 GiB
mmc0: Got data interrupt 0x00000002 even though no data operation was in progress.
mmcblk0: p1
 
.........
 
mmc1: new high speed SDHC card at address aaaa
mmcblk1: mmc1:aaaa SU08G 7.40 GiB
mmcblk1: p1
Boot log for EMMC
mmc0: BKOPS_EN bit is not set
mmc0: new high speed MMC card at address 0001
 
mmcblk0: mmc0:0001 MMC04G 3.57 GiB
mmcblk0boot0: mmc0:0001 MMC04G partition 1 2.00 MiB
mmcblk0boot1: mmc0:0001 MMC04G partition 2 2.00 MiB
mmcblk0rpmb: mmc0:0001 MMC04G partition 3 128 KiB
 
mmcblk0:
 
mmcblk0boot1: unknown partition table
mmcblk0boot0: unknown partition table

Mainline Status

The SD driver is currently in sync with mainline kernel 4.9 except the below changes
  • add support for switching to UHS-I modes on ZynqMP Platform

Change Log

2016.3
Summary:
  • Added support for Tap delays required for 3.0 modes and high speed modes.
  • Added new workaround for auto tuning.
  • Added "SDHCI_QUIRK_BROKEN_ADMA" quirk to the sdhci arasan controller based on DT property. With 4.6 kernel ADMA2 is broken on Zynq, so added this quirk as a workaround and can be reverted once it is fixed.
Commits:
0fb3161d0a60 - mmc: sdhci-of-arasan: Add support for tapdelay programming
ba35b69e41d0 - mmc: sdhci-of-arasan: Added workaround for auto tuning
0e4e40714931 - mmc: arasan: Add ADMA broken quirk based on DT parameter

2016.4
Summary:
  • None

2017.1
Summary:
  • Add pinctrl support to the driver
Commits:
3feb3b18c249 - mmc: arasan: Add pinctrl support to the driver

2017.2
Summary:
  • None

2017.3
Summary:
  • Added support for switching to UHS-I modes on ZynqMP Platform
  • Reverted "mmc: arasan: Add ADMA broken quirk based on DT parameter"
Commits:
dcbfca5021bb - sdhci: add support for switching to UHS-I modes on ZynqMP Platform
f9658a41c361 - Revert "mmc: arasan: Add ADMA broken quirk based on DT parameter"

2017.4
Summary:
  • None

2018.1
Summary:
  • None

2018.2
Summary:
  • Removed quirk for broken base clock in SDHCI driver
  • Added runtime PM support in SDHCI driver
Commits:
f18d4e43c908 - Remove quirk for broken base clock
f7225b8f1108 - Add runtime PM support

Related Links

Source file link:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/mmc/host/sdhci-of-arasan.c