Introduction

This page gives an overview of gpiops driver which is available as part of the Xilinx Vivado and SDK distribution.
The Xilinx General purpose I/O is a collection of input/output pins available to the software application running on Processing system.

How to enable

Source Path for the driver can be found at
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/gpiops

Driver source code is organized into different folders. Below diagram shows the gpiops driver source organization
gpiops
|
- doc - Provides the API and data structure details
|
- examples - Reference application to show how to use the driver APIs and calling sequence
|
- src - Driver source files

Features Supported in the driver

Controller Features

ZYNQMP

  • 78 GPIO signals for device pins.
    • Routed through the MIO multiplexer.
    • Outputs are 3-state capable.
  • 288 GPIO signals between the PS and PL through the EMIO interface.
    • 96 inputs.
    • 192 outputs (96 true outputs and 96 output enables).
  • I/O interface is organized into 6 banks(3 MIO and 3 EMIO)
  • Interface control registers are grouped by bank {0:5}.
  • Input values are read using the six DATA_RO_x registers.
  • The function of each GPIO can be dynamically programmed on an individual or group basis.
  • Enable, bit or bank data write, output enable and direction controls.
  • Programmable interrupts on individual GPIO basis.
    • Status read of raw and masked interrupt.
    • Selectable sensitivity: Level-sensitive (High or Low) or edge-sensitive (positive, negative, or both).

ZYNQ

  • 54 GPIO signals for device pins
    • Routed through the MIO multiplexer.
    • Outputs are 3-state capable.
  • 192 GPIO signals between the PS and PL via the EMIO interface.
    • 64 Inputs
    • 128 Outputs(64 true outputs and 64 output enables).
  • The function of each GPIO can be dynamically programmed on an individual or group basis.
  • Enable, bit or bank data write, output enable and direction controls.
  • Programmable interrupts on individual GPIO basis.
    • Status read of raw and masked interrupt.
    • Selectable sensitivity: Level-sensitive (High or Low) or edge-sensitive (positive, negative, or both).

Driver Features

The Gpiops Standalone driver support the below things.
  • All controller features supported.

Known Issues and Limitations

  • None

Test cases

  • Refer below path for testing different examples for each feature of the IP.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/gpiops/examples
  • xgpiops_intr_example.c : This example shows the usage of the driver in interrupt mode. It uses the interrupt capability of the GPIO to detect push button events and set the output LED based on the input.
  • xgpiops_polled_example.c : This example provides the usage of API's for reading/writing to the indiviual pins.

Change Log

2017.1
Summary:
  • Fixed compilation warnings.
  • Added readme.txt file to generate doxygen for examples.
Commits:
  • d0324be : Fixed compilation warnings
  • fadfb8a : Added readme.txt file to generate doxygen for examples

2017.2
Summary:
  • Added tab space for return statements in functions
  • Added notes about gpio pin description in examples.
Commits:
  • 9bd47ee : Added tabspace for return statements in functions
  • 0ed0f32 : Added notes about gpio pin description in examples

2017.3
Summary:
  • Updated the source files to updated addtogroup version numbers.
Commits:
  • 04cf58b : Updated the source files to updated addtogroup version numbers

2017.4
  • None