Zynq features four clocks, the FCLKs, which are routed into the PL. In a Linux based system device drivers are expected to be clock aware and take ownership of their clocks and gate/ungate and change frequencies on their own discretion. For these purposes Linux features the 'Common Clock Framework'. Please refer to Linux kernel documentation and sources for more information about this.

However, legacy IP might not yet be ported to use the CCF. For this reason and some quick bring up and debug purposes, the FCLK controls are also exposed to userspace in sysfs through the Xilinx 'device config' driver. This functionality has been added to the Xilinx Linux kernel with commit 'char: xdevcfg: Allow userspace fclk controls' (sha1: fc6331bb4f0a73ce94580892e456378ceea8404f).

Sysfs Interface Description

The files fclk_export and fclk_unexport are created under the devcfg
device node in sysfs. Reading those files returns the valid values to
write to the corresponding file.

Writing a valid value to fclk_export exports clock controls for the
chosen clock in the fclk subdirectory. Similarly, writing a valid
value to fclk_unexport reverts the export.

Currently the CCF API functions clk_enable/clk_disable,
clk_round_rate and clk_set_rate are exported (clk_(un)prepare is
implicitly done during (un-)export).

Writing non-zero to this file enables the clock. Writing zero disables it.

Writing a frequency in Hz to it sets the frequency to be rounded.
Reading the file prints the set frequency and the rounded frequency.

Reading this file returns the current clock frequency. Writing sets a
new frequency.

Related Links

Zynq Power Management
A common clock framework (lwn.net)