Introduction

This page gives an overview of CSUDMA driver which is available as part of the Xilinx Vivado and SDK distribution.
CSUDMA Provides efficient transfer of Data between the PSS's Memory and the CSU Stream Peripherals.

The CSU_DMA is present inside CSU (Configuration Security Unit) module which is located within the Low-Power Subsystem (LPS) internal to the PS.
CSU_DMA allows the CSU to move data efficiently between the memory (32 bit AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure
Stream Switch (SSS). The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC (read) channel and DST (write) channel. The DMA is effectively able to transfer data:
- From PS-side to the SSS-side (SRC DMA only)
- From SSS-side to the PS-side (DST DMA only)
- Simultaneous PS-side to SSS_side and SSS-side to the PS-side

How to enable

Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/csudma

Driver source code is organized into different folders. Below diagram shows the csudma driver source organization

CSUDMA
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

.

Features Supported

Controller Features

  • Simple DMA, no scatter-gather
  • Separate read channel (SRC) and write channel(DST) DMA
  • Read channel fetches data from the PS-side(memory) and delivers it to the CSU secure stream switch (SSS) interface
  • Write channel receives data from the CSU secure stream switch (SSS) interface and delivers it to the PS-side (memory).
  • 32-bit AXI 3.0 interface on the PS-side
  • Deep 128x32-bit data FIFOs for both the SRC and DST data paths
  • PS-side AXI Issuing capability up to a maximum of 9 commands per channel, with programmable maximum
  • Single thread (AXI-ID) operation for both read and write channels
  • CSU_DMA operates synchronously in the “csu_main_clk” domain
  • Target CSU_DMA frequency of 400MHz max
  • DST DMA will only issue a write AXI command if the corresponding write data is available in the write data FIFO – Store and Forward.
  • SRC DMA wil only issue a read AXI command if there is enough space in the read data FIFO for the entire burst.
  • DMA start address is 32-bit aligned
  • DMA transfer length is in units of 4-byte words
  • DMA can accept only 1 command per channel
  • Timeout mechanisms for both SRC(read) and DST(write) channels
  • Automatic hardware management of 4kbyte boundary crossing on the PS-side (AXI )
  • Dedicated APB interface for CSU_DMA register access
  • Always generates secure (AxPROT[1]=0) AXI commands
  • DMA supports INCR and FIXED (keyhole) AXI burst-types
  • Zero-ization of FIFOs for securioty purposes achieved via RAM MBIST
  • Byte endianness option available for the SRC DMA
  • Pseudo-CRC option available for the SRC DMA paylaod

Standalone Driver Supported Features

The CSUDMA Standalone driver support the below things.
  • All Controller Features supported.

Test cases

  • Refer below pah for testing differnet examples for each feature of the IP.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/csudma/examples

xcsudma_selftest_example.c – It includes few basic core API testing for self-test.
xcsudma_polled_example.c – This is a polled mode example in which a CSUDMA busy state is polled.
xcsudma_intr_example.c – This is an interrupt mode example in which process done interrupt has to be generated to come out of loop.

Known issues and Limitations

  • None.

Change Log

2018.2
  • None
2018.1
  • Added Support for peripheral test app support
  • Added New API XCsuDma_64BitTransfer() in the driver which is useful
for 64-bit dma address transfers through pmu processor.
Commit Id's:
7a29060: Add Support for peripheral test app support
3f65d71: Add New API XCsuDma_64BitTransfer() in the driver which is useful for 64-bit dma address transfers through pmu processor.
2017.4
  • None
2017.3
  • None
2017.2
  • None
2017.1
  • None
2016.4
  • None
2016.3
  • None

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