Introduction

This page gives an overview of bram (block ram comtroller) driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/bram

Driver source code is organized into different folders. Below diagram shows the bram driver source organization

bram
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

Features Supported

Controller/Driver features supported


The Xilinx BRAM controller is a soft IP core designed for Xilinx FPGAs and contains the following general features,
  • LMB v2.0 bus interfaces with byte enable support
  • Separate read and write channel interfaces to utilize dual port FPGA BRAM technology
  • Supports memory sizes up to a maximum of 2 MBytes
  • Compatible with Xilinx AXI Interconnect
  • Used in conjunction with bram_block peripheral to provide fast BRAM memory solution for MicroBlaze ILMB and DLMB ports
  • Supports byte, half-word, and word transfers
  • Supports optional BRAM error correction and detection

Known issues and Limitations

None

Test cases

BRAM selftest example

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/bram/examples/xbram_example.c
This example initializes ECC for BRAM and executes the selftest.
Output
Successfully ran Bram Example

BRAM interrupt example

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/bram/examples/xbram_intr_example.c
This example configures interrupt for BRAM controller and evaluates triggering of interrupt through fault injection
Output
Successfully ran Bram Interrupt Example

Changelog


2017.4


  • No Changes

2017.3

  • Updated bram.tcl to add U suffix for all the macros exported into xparameters.h
  • Fixed compilation warnings in the driver

Related Links

The Xilinx BRAM controller is a soft IP core designed for Xilinx