LLFIFO Standalone Driver


Introduction
This page gives an overview of llfifo driver which is available as part of the Xilinx Vivado and SDK distribution.

The LogiCOREā„¢ IP AXI4-Stream FIFO core allows memory mapped access to a AXI4-Stream interface.
The core can be used to interface to AXI Streaming IPs, Similar to the LogiCORE IP AXI Ethernet core,
Without having to use a full DMA solution. The principal operation of this core allows the write or read
Of data packets to or from a device without any concern over the AXI4-Stream interface signaling.
You can easily manage the AXI4-Stream interfaces as they are transparent.

How to enable

Source Path for the driver
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/llfifo

Driver source code is organized into different folders. Below diagram shows the llfifo driver source organization

LLFIFO
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

Features Supported

Controller Features

  • 32-bit AXI4-Lite slave interface
  • Configurable data interface type (AXI4 or AXI4-Lite)
  • Configurable data width of 32, 64, 128, 256 or 512 bits (AXI4 Data Interface only). For AXI4-Lite, the FIFO data width is 32 bits and for AXI4, it is identical to AXI4 data width.
  • Configurable FIFO depth of 512 to 128k locations.
  • Independently configurable internal TX and RX data FIFOs
  • Full duplex operation
  • Supports AXI Ethernet basic mode
  • Provides interrupts for error and status conditions
  • TX and RX cut-through mode

Standalone Driver Supported Features

The LLFIFO Standalone driver support the below things.
  • Supports Configurable data interface types (AXI4 or AXI4-lite).
  • Supports Configurable data widths
  • Supports Configurable FIFO depth feature
  • Supports TX and RX cut-through mode feature
  • Supports Independent configuration of the Tx and Rx data FIFO's.
  • Supports Full duplex operation.

Test cases

  • Refer below pah for testing different examples for each feature of the IP.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/llfifo/examples

xllfifo_interrupt_example.c : This example is the interrupt example for the FIFO it assumes that at the
H/w level FIFO is connected in loopback. In these we write known amount of data to the FIFO and wait for interrupts and after
Completely receiving the data compares it with the data transmitted.

xllfifo_polling_example.c : This example is the polling example for the FIFO it assumes that at the h/w level FIFO is connected in
Loopback. In these we write known amount of data to the FIFO and Receive the data and compare with the data transmitted.

Known issues and Limitations

  • All IP features are supported by the driver.

Change Log

2017.3
  • Fixed doxygen issues in the driver
  • Updated comments in the usage section in the driver header file.
Commit Id's:
5d24a0b : llfifo: Fix doxygen issues in the driver
3197d3a : llfifo: Updated comments in the usage section
2017.4
  • None

Related Links