AXI VDMA Standalone Driver


Introduction
This page gives an overview of axi vdma driver which is available as part of the Xilinx Vivado and SDK distribution. The Xilinx® LogiCORE™ IP AXI VDMA core is a soft IP core. It provides high-bandwidth direct Memory access between memory and AXI4-Stream video type target peripherals including peripherals which support the AXI4-Stream Video protocol as described in the Video IP:AXI Feature Adoption section of the Vivado AXI Reference Guide (UG1037)

Source Path for the driver
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axivdma

Driver source code is organized into different folders. Below diagram shows the axivdma driver source organization
AXI VDMA

├── data Provides the API and data structure details


├── examples Reference application to show how to use the driver APIs and calling sequence


└── src Driver source files


Features Supported

Controller Features

  • AXI4 Compliant
  • Primary AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits
  • Primary AXI4-Stream data width support of multiples of 8 up to 1,024 bits
  • Optional Data Realignment Engine
  • Optional Genlock Synchronization
  • Independent, asynchronous channel operation
  • Dynamic clock frequency change of AXI4-Stream interface clocks
  • Optional frame advance or repeat on error
  • Supports up to 32 frame buffers
  • Supports up to 64-bit address space

Standalone Driver Supported Features

The AXI VDMA Standalone driver supports the below things.
  • Supports 64-bit Addressing
  • Supports Gen-Lock Synchronization
  • Supports up to 32 frame buffers
  • Supports frame advance or repeat on error
  • Supports Parking Mode
  • Supports Circular Buffer Mode

Test cases

  • Refer below pah for testing different examples for each feature of the IP.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axivdma/examples

xaxivdma_example_selftest.c : This example does a basic reset of the core and checks core is coming out of reset or not.
xaxivdma_example_intr.c : This example demonstrates how to use the AXI Video DMA with other video IP's to do video transfer.This example won't work by itself it needs two other video IP's, One for writing frames to memory and one for reading the video frames from memory
vdma.c and vdma_api.c : This example demonstrates how to use triple frame buffer feature in the AXI Video DMA

Known issues and Limitations

  • When H/w is configured without DRE driver will throw an error if the user sends an unaligned buffer address.
  • User application should handle buffer address alignment in case h/w is configured without DRE

Change Log

2018.2
  • None
2018.1
  • Fix compilation error in selftest example
  • Align default TX/RX framebuffer count with IP configuration
Commit Id's
63368d9 vdma: Align default TX/RX framebuffer count with IP configuration
a3d2180 axivdma: Fix compilation error in selftest example

2017.4
  • None
2017.3
  • None
2017.2
  • None
2017.1
  • Fixed compilation errors in the driver when compiled the driver with C++ compiler
  • Modified text file to generate doxygen for examples
Commit Id's
578c86f : Fixed compilation errors in the driver when compiled the driver with C++ compiler
e9b7aed : Modified text file to generate doxygen for examples

Related Links