Introduction

This page gives an overview of axi mcdma driver which is available as part of the Xilinx Vivado and SDK distribution.

The Xilinx® LogiCORE™ IP AXI MultiChannel Direct Memory Access (AXI MCDMA) core is a soft Xilinx IP core for use
with the Xilinx Vivado® Design Suite. The AXI MCDMA provides high-bandwidth direct memory access between memory and
AXI4-Stream target peripherals. The AXI MCDMA core provides Scatter Gather interface with Multiple Channel support with independent configuration.

How to enable

Source Path for the driver
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mcdma

Driver source code is organized into different folders. Below diagram shows the axicdma driver source organization

AXI MCDMA
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

Features Supported

Controller Features

  • AXI4 Compliant
  • AXI4 data width support of 32, 64, 128, 256, 512 and 1,024 bits
  • AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits
  • Supports up to 16 independent Channels
  • Supports per Channel Interrupt output
  • Supports DRE alignment for Streaming data Width of up to 512 bits
  • Supports up to 64MB transfer per BD
  • Optional AXIS Control and Status Streams

Standalone Driver Supported Features

The AXI MCDMA Standalone driver supports the following:
  • Supports upto 16 Channels
  • Supports Scatter/Gather Direct Memory Access (DMA)
  • Supports 64-bit Addressing
  • Supports Optional Data Re-Alignment Feature
  • Supports per channel interrupt
  • Supports AXIS Control and Status Streams.

Test cases

  • Refer below pah for testing different examples for each feature of the IP.
xmcdma_interrupt_example.c: This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in interrupt mode.
xmcdma_polled_example.c: This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in polled mode

Known issues and Limitations

  • All IP features are supported

Change Log

2017.3:
  • Added support for MCDMA IP
Commit ID:
6b7af95 : Initial version of the driver
2017.4:
  • None.

Related Links