AXI Ethernet Standalone Driver


Introduction

This page gives an overview of axi ethernet driver which is available as part of the Xilinx Vivado and SDK distribution.
The Xilinx® AXI Ethernet Subsystem implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. This core supports the use of MII, GMII, SGMII, RGMII, and 1000BASE-X interfaces to connect a media access control (MAC) to a Physical-side interface (PHY) chip. It also provides an on-chip PHY for 1G/2.5G SGMII and 1000/2500 BASE-X modes. The MDIO interface is used to access PHY Management registers. This subsystem optionally enables TCP/UDP full checksum Offload, VLAN stripping, tagging, translation and extended filtering for multicast frames features.

How to enable

Source Path for the driver
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axiethernet

Driver source code is organized into different folders. Below diagram shows the axi_ethernet driver source organization
AXI Ethernet
|
-- doc - Provides the API and data structure details
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- examples - Reference application to show how to use the driver APIs and calling sequence
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- source - Driver source files

Features Supported

Controller Features

  • Support for MII, GMII, RGMII, SGMII, and 1000BASE-X PHY interfaces
  • Support for 1000BASE-X and SGMII over Select Input/Output (I/O) Low Voltage Differential Signaling (LVDS)
  • Support for pause frames for flow control
  • Media Independent Interface Management (also called as MII), is used for accessing the PHY registers
  • Ethernet Audio Video Bridging (AVB) support
  • AXI4-Stream transmit/receive interface
  • Support for 2.5G Ethernet. This feature is enabled for the following devices: Kintex®-7, Virtex®-7 with GTH and GTX transceivers Artix®-7 devices with GTP and speed grade -2 and -3 UltraScale™, UltraScale+™ devices with GTH and GTY transceivers
  • IEEE Standard 1588 Support
  • AXI4-Lite register interface

Standalone Driver Supported Features

The AXI Ethernet Standalone driver supports the below things.
  • Supports all 1G phy-interface types MII, GMII, RGMII, SGMII and 1000base-x
  • Supports VLAN Frames
  • Supports Pause frames and flow control features
  • Support for AXI DMA Ethernet-based designs
  • Support for Axi Ethernet FIFO based designs
  • Support for Axi MCDMA Ethernet-based designs
  • Supports different Speeds 10/100/1000 Mbps
  • Supports Partial/Full Checksum offloading
  • Supports 2.5G buffered mode feature.

Features not supported

  • IEEE 1588 feature is not supported
  • No Support when 2.5G Ethernet is configured for Non-Buffered/Processor mode
  • No Support when 1G Ethernet is configured in Non-Buffered/Processor Mode

Interop

- PHY device Marvell 88E1116 has been tested on KC705 evaluation board
- PHY device TI DP83867 SGMII have been tested on VCU118 board.

Test cases

Axi Ethernet DMA Example
Axi Ethernet basic AXI DMA loop-back example can be tested by selecting xaxiethernet_example_intr_sgdma.c, xaxiethernet_example_util.c and xaxiethernet_example.h from the driver.
Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axiethernet/examples/readme.txt for more information.

Axi Ethernet FIFO Example
Axi Ethernet basic AXI FIFO loop-back example can be tested by selecting xaxiethernet_example_intr_fifo.c, xaxiethernet_example_util.c and xaxiethernet_example.h from the driver.
Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axiethernet/examples/readme.txt for more information.

Known Issues/Limitations

  • At the h/w level if the MAC reference clock is driving from onboard clock oscillator e.g si570 or si5324
Make sure clock is programmed to the proper clock value before performing any operations on the MAC.

Changelog

2018.2
  • None
2018.1
  • Fix compilation issues in multicast/extvlan example.
  • Set num of multicast table entries parameter based on hw design.
  • Use table entries count from config structure.
  • Used UINTPTR type for DMA BaseAddress.
  • Implementing poll timeout API in the axiethernet driver.
4ea9f9d axiethernet: Fix compilation issues in multicast/extvlan example
5fa4d74 Set num of multicast table entries parameter based on hw design
abe45ad axiethernet: Use table entries count from config structure
ee523e1 axiethernet: Used UINTPTR type for DMA BaseAddress
1866fc8 Axiethernet: Implementing poll timeout API in the axiethernet driver
2017.4:
  • None.
2017.3
  • Added support for Ethernet MCDMA Configuration in the driver
  • Added axi ethernet mcdma examples.
  • Fixed issues with Chipscope designs
  • Fix pmufw compilation errors for Ethernet mcdma based designs.
Commit ID's
60104ac : axiethernet: Add support for mcdma
2ad67e6 : axiethernet: Add axiethernet mcdma examples
14c3ca9 : axiethernet: Fix issues with the chipscope designs
2e47d70 : axiethernet: Fix pmufw compilation errors
2017.2
  • Increase timeout values in the driver as per new h/w updates for ultrascale+ devices
Commit ID
ef2ffba: Increase timeout values
2017.1
  • Added Support for TI PHY (DP83867)
Commit ID
a523a1d : Add Support for TI PHY in the peripheral test

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