2016.3 Linux Release Notes


Feature Changes
Module Name
Driver Location
Feature Changes
Link
Linux kernel
Linux kernel Source
  • Upgrade from 4.4. to 4.6.
https://kernelnewbies.org/Linux_4.6
AXIDMA
AXICDMA
AXIVDMA
drivers/dma/xilinx/xilinx_dma.c
  • Previously available separate drivers for AXIDMA, AXICDMA, and AXIVDMA are combined into a single driver and the older drivers are deleted.
  • The combined driver is mainlined and is available in 4.6 kernel.
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
ZDMA
drivers/dma/xilinx/zynqmp_dma.c
  • The driver got accepted in mainline and will be available in Linux 4.8. The Xilinx 2016.3 driver is synced up with the mainline driver.
  • Added support for scatter-gather transfers in DMA test client for ZDMA.
  • Deleted previously available zDMA test client driver. The common DMA test client driver is now used for zDMA.
http://www.wiki.xilinx.com/Zynqmp+DMA
SD Controller (for Zynq and ZynqMP)
drivers/mmc/host/sdhci-of-arasan.c
  • Added support for programming tap delays for ZynqMP. This applies for UHS speed class. A new compatibility string was added through Device Tree for the same.
http://www.wiki.xilinx.com/SD+controller
PS Ethernet MAC (Zynq and ZynqMP)
drivers/net/ethernet/cadence/macb.c
  • Added support for 64 bit descriptors. This adds support for 64 bit addressing.
  • Added support for MDIO PHY nodes to enable use of gmii2rgmii converter.
http://www.wiki.xilinx.com/Macb+Driver
GQSPI (ZynqMP)
drivers/spi/spi-zynqmp-qspi.c
  • Added support for programming tap delays for higher frequencies.
http://www.wiki.xilinx.com/Linux+ZynqMP+GQSPI+Driver
SERDES (ZynqMP)
drivers/phy/phy-zynqmp.c
  • Added support for SGMII. This change will ensure PS Ethernet driver (macb) can operate at SGMII mode.
  • Added a separate function to bypass scrambler/de-scrambler and encoder/decoder feature. This makes SATA misc settings to use scrambler/de-scrambler and encoder/decoder functions.
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
FPGA Manager (for ZynqMP)
drivers/fpga/zynqmp-fpga.c
  • Added FPGA manager support for ZynqMPSoC.
http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming#x-Programming%20the%20PL%20through%20Linux
Common Clock Framework (ZynqMP)
drivers/clk/zynqmp
  • Added support for common clock framework. This includes necessary device tree binding support.
http://www.wiki.xilinx.com/Common+Clock+Framework


Bug Fixes
Module Name
Driver Location
Bug Fixes
Link
AXIDMA/AXICDMA/AXIVDMA
drivers/dma/xilinx/xilinx_dma.c
  • Fix provided for a race condition in VDMA that prevents submitting a descriptor to the active list while VDMA engine is in progress.
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
AxiEthernet
drivers/net/ethernet/xilinx/xilinx_axienet_main.c
drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
drivers/net/ethernet/xilinx/xilinx_axienet.h
  • Fix provided for a kernel crash on 64 bit platforms. The variable ptp_tx_skb for struct axidma_bd in filedrivers/net/ethernet/xilinx/xilinx_axienet.h that stores the skb address was of type u32 which was causing the crash. This is now changed to type phys_addr_t.
http://www.wiki.xilinx.com/Linux+AXI+Ethernet+driver
SD Controller (Zynq and ZynqMP)
drivers/mmc/host/sdhci-of-arasan.c
  • Modified the SD standard speed only for ZynqMPSoC from 25 MHz to 19 MHz. When level shifters are in use, the timing was met for 19 MHz (and not 25 MHz). Hence this change is required. A quirk SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN is added for this purpose.

  • Few class 10 SD memory cards were showing the error message "Got data interrupt even though no data operation in progress". Fix for the same was provided by using the quirk "SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12". to enable auto cmd12 support.
  • Modified the work around for auto tuning mode as suggested by the internal verification team.
  • Fix provided to use SDMA rather than ADMA for Zynq. With 4.6 kernel there were stability issues for using ADMA. This is a temporary workaround only for 4.6 kernel and will be reverted back for later releases. For later kernel versions this issue is not seen for ADMA.
http://www.wiki.xilinx.com/SD+controller
PS Ethernet MAC (Zynq and ZynqMP)
drivers/net/ethernet/cadence/macb.c
  • Fix provided to handle HRESP error. Upon HRESP error, a SW reset of Rx and Tx paths are done with re-initialization of descriptors and Rx and Tx queue pointers.
  • Fix provided to use the correct capability masks for JUMBO and TSU.
  • Update TX and RX EXT BD registers using a check because they are only relevant in case of 1588 timestamping.
http://www.wiki.xilinx.com/Macb+Driver
SERDES (ZynqMP)
drivers/phy/phy-zynqmp.c
  • Made changes to use correct swing and pre-emphasis values as per the DP workaround documentation.
  • Made changes to reset the swing control and de-emphasis for DP. When a PHY lane is initialized for DP, the de-emphasis and swing control must be reset to override the values from DP with the values programmed in the register.
  • Change made to use ICM_CONFIG1 instead of ICM_CONFIG0. This fixes PMOS calibration issue for PCIe.
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
USB (ZynqMP)
drivers/usb/dwc3
  • Change provided to fix kernel hang during unbinding of USB. Change made to call_platform_depopulate before clock disabling.
  • Changes made to fix kernel warnings during unbinding of USB.
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+USB+device+driver
Devcfg (Zynq only)
drivers/char/xilinx_devcfg.c
  • Change made to add extra checking to prevent an user space application to flash a fpga that was created for another chip.
http://www.wiki.xilinx.com/Solution+Zynq+PL+Programming
PS UART (Zynq and ZynqMP)
drivers/tty/serial/xilinx_uartps.c
  • Fix provided to wait for Rx and Tx reset done status after issuing a reset.
http://www.wiki.xilinx.com/PS+UART
AXI GPIO
drivers/gpio/gpio-xilinx.c
  • Change made to use readl/writel for ARM64 instead of __raw versions.
  • Changes made to fix driver compilation warnings.
http://www.wiki.xilinx.com/AXI+GPIO

Answer Records (ARs)
Module Name
AR Title
AR Link
ZynqMP Reset Controller
The Zynq Multi-Processor reset-controller has the ability to reset lines connected to different blocks and peripherals (LPD & FPD blocks) in the SoC
https://www.xilinx.com/support/answers/68058.html
PS Ethernet MAC (Zynq and ZynqMP)
2016.3 PetaLinux - Error message during bootup "[Firmware Warn]: /amba/ethernet@e000b000/mdio/phy@7: Whitelisted compatible string. Please remove"
https://www.xilinx.com/support/answers/68095.html
APM
2016.3 PetaLinux Zynq UltraScale+ MPSoC AXI Performance Monitor (APM) sample clock via Common Clock Framework (CCF)
https://www.xilinx.com/support/answers/68077.html
Xilinx DMAs
2016.3 PetaLinux - Zynq UltraScale+ MPSoC: During Linux boot up, warning messages are generated [ 5.001929] xilinx-zynqmp-dma ffa80000.dma: main clock not found
https://www.xilinx.com/support/answers/68118.html
Power Management
2016.3 PetaLinux Zynq UltraScale+ MPSoC Power Management in NAND Linux driver
https://www.xilinx.com/support/answers/68078.html